AMD Receives All Necessary Approvals for Proposed Acquisition of Xilinx
AMD (NASDAQ: AMD) today announced that it has received approval from all necessary authorities to proceed with the acquisition of Xilinx, Inc. (NASDAQ: XLNX).
Vendor:
Xilinx, Inc.
Category:
Arithmetic Units
Adder/Subtracter
The Adder/Subtracter IP provides LUT and single DSP48 slice add/sub implementations.
Overview
The Adder/Subtracter IP provides LUT and single DSP48 slice add/sub implementations. The Adder/Subtracter module can implement adders (A+B), subtracters (A–B), and dynamically configurable adder/subtracters which operate on signed or unsigned data. The function can be implemented in a single DSP48 slice or LUTs. The module can be pipelined.
Key features
- Generates adder, subtracter and add/subtracter functions
- Supports two’s complement-signed and unsigned operations
- Supports fabric implementation inputs ranging from 1 to 256 bits wide
- Supports DSP48 slice implementation with inputs up to 48 bits wide
- Optional carry input and output.
- Optional clock enable and synchronous clear
- Optional bypass (loud) capability
- Option to set the B Value to a constant
- Optional pipelined operation
- For use with Xilinx Vivado® IP Catalog, Xilinx AccelDSP™ Synthesis Tool, and Xilinx System Generator.
Specifications
Identity
Part Number
Adder/Subtracter
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Arithmetic Unit IP cores
What is Adder/Subtracter?
Adder/Subtracter is a Arithmetic Units IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Arithmetic Units?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Arithmetic Units IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.