Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)
The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructi…
High performance Linux capable vector processor
The SiFive Intelligence VIU75 Standard Core is a single-core instantiation of our RISC-V application processor with vector extens…
DVB-S2X NarrowBand Demodulator IP
This is NarrowBand demodulator IP is silicon proven and extratced from production chipsets, it performs demodulation according to…
U74-MC Multicore: four U74 cores and one S76 core
The SiFIve U74-MC Standard Core is the world's highest performance RISC-V application processor, capable of supporting full-featu…
U74 High performance Linux-capable RISC V processor
The SiFive U74 Standard Core is a single-core instantiation of the world's highest performance RISC-V application processor, capa…
S76 MC Quad-core 64-bit embedded processor
The SiFive S76-MC Standard Core is a high-performance 64-bit quad-core embedded processor which is fully-compliant with the RISC-…
S76 High-performance 64-bit embedded core
The SiFive S76 Standard Core is a high-performance 64-bit embedded processor which is fully-compliant with the RISC-V ISA.
S54 64-bit embedded RISC V processor
The SiFive S54 Standard Core is a 64-bit embedded processor that is fully-compliant with the RISC-V ISA.
S51 Low-power 64-bit MCU RISC V core
The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA.
S21 Area optimized 64-bit RISC V processor
The SiFive S21 Standard Core is a full-featured 64-bit embedded processor based on the S2 Series.
Half precision, IEEE 754, floating point fused multiply add
The eSi-HP-FP-Fused-Multiply-Add IP core implements half-precision (16-bit), IEEE 754 compliant, floating-point fused multiply an…
Single precision, IEEE 754, floating point to integer conversion
The eSi-SP-FP-Float-to-Int IP core implements single-precision (32-bit), IEEE 754 floating-point to integer conversion.
Single precision, IEEE 754, floating point square root
The eSi-SP-FP-Square-Root IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point square root operations.
Single precision, IEEE 754, floating point divider
The eSi-SP-FP-Divider IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point division.
Single precision, IEEE 754, floating point multiplier
The eSi-SP-FP-Multiplier IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point multiplication.
Single precision, IEEE 754, floating point adder
The eSi-SP-FP-Adder IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point addition and subtraction ope…
64-bit RISC-V microcontroller. Small core for 64-bit applications.
64-bit RISC-V core.
64-bit CPU with RISC-V Vector Extension
The 64-bit NX27V is a vector processor with 5-stage scalar pipeline that supports the latest RISC-V specification, including the …
TPU IoT/Edge Licensable Hardware IP
The Prodigy is the first Universal Processor combining General Purpose Processors, High Performance Computng (HPC), Artficial Int…
Compact High-Speed 32-bit CPU Core with MemBoost and PMA
The 32-bit A27 is a 5-stage processor that supports the latest RISC-V specification, including "G" ("IMAFD") standard instruction…