SCR6 is a high-performance, silicon-proven, 64-bit RISC-V processor core.
SCR6 is a high-performance, silicon-proven, 64-bit RISC-V processor core. It is optimized for embedded RTOS-based applications, that require considerable computational power.
The SCR6 core supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, "B" Bit Manipulation, and "K" Scalar Cryptography extensions. SCR6 includes an out-of-order superscalar 12-stage pipeline, a high-precision floating-point unit, a branch prediction unit, PLIC or APLIC units for efficient interrupt processing, and industry-standard AXI4 and JTAG interfaces providing flexibility and compatibility.
The SCR6 memory subsystem includes L1 and L2 caches and a PMP unit that provide the execution of RTOS-based operating systems. The processor core can operate in heterogenous multicore (up to 8 cores in a cluster) environments, offering hardware-level support for memory coherency and simplified external accelerators' integration.
SCR6 Key Features
| Core | |
|---|---|
| ISA | RV64GC[B][K], Bit Manipulation [B], Scalar Cryptography Instructions [K] — optional |
| Pipeline | Out-of-order 12-stage superscalar |
| Floating-Point Unit (FPU) | Single/Double-precision, IEEE 754-2008 standard |
| Multicore Support (SMP) | Up to 8 cores with cache coherency |
| Branch Prediction Unit (BPU) | Static/Dynamic |
| Memory Subsystem | |
| L1 Cache | Up to 64KB + 64KB, error protection — parity/ECC |
| L2 Cache | From 128KB to 2MB, error protection — ECC |
| Physical Memory Protection Unit (PMP) | Configurable, up to 32-region PMP |
| Interrupt Subsystem | |
| Platform-level interrupt controller (PLIC) | Up to 1023 interrupt lines, up to 256 priority levels |
| Advanced Interrupt Architecture (AIA) | Advanced platform level interrupt controller (APLIC) + Incoming Message Signaled Interrupt Controller (IMSIC) up to 1023 interrupt lines, up to 2047 distinct interrupt identities at each hart |
| Debug Subsystem | |
| Interface | JTAG/cJTAG-compliant interface |
| Breakpoints | Up to 8 hardware breakpoints, unlimited software breakpoints support |
| Interfaces | |
| AXI | Master AXI4 AMBA standard interface |
| External Ports | TCM AXI slave port, L2 cache coherency port |
| Timers and Counters | |
| Performance Monitoring | Up to 32 performance counters |
| Embedded 64-bit RTC Timer | Machine-mode timer interrupt support |
Development Tools
Syntacore Development Toolkit (SCR6 Optimized)
The SC-DT package is a ready-to-use software development kit containing pre-built and pre-configured tools that simplify software development for the SCR6 core. With SC-DT, you can take advantage of the pre-built tools and configurations, reducing the time and effort required to get up and running with SCR6. SC-DT supports Windows and Linux operating systems and includes:
Syntacore also supports and maintains the Zephyr operating system that is not part of the SC-DT package and is downloadable separately.
SCR6 is available out-of-the-box, configurable, written in SystemVerilog and comes with a full set of pre-built, tested, and optimized development tools, pre-configured FPGA-based SDK and complete documentation. The software package includes ready-to-use toolchains, IDEs, operating systems, bootloaders, debuggers, simulators, and sample projects that reduce the time and effort required to get up and running with SCR6.
The SCR6 product package includes:
Note: some files may require an NDA depending on provider policy.
High-performance microcontroller core with a 12-stage dual-issue out-of-order pipeline and a high performance FPU is a MCU IP core from Syntacore listed on Semi IP Hub.
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