Overview
The SiFive U84 Standard Core is a single-core instantiation of our most scalable out-of-order RISC-V application processor, and is capable of supporting full-featured operating systems such as Linux.
The U84 is feature rich and architected for high performance/area or watt, making it ideal for various target markets (e.g., edge/autonomous, enterprise/networking and consumer markets).
The U8 Series features SiFive’s maximum performance RISC-V Linux-capable application processor. The U8 core has a 3 issue out-of-order superscalar with support for virtual memory. The U8 Series provides unprecedented scalability and is optimized for the highest performance per watt. This makes it ideal for applications such as edge compute, 5G base stations and AR/VR/MR.
Learn more about CPU IP core
How embedded RISC-V processors in NICs, retimers, optics, switches, and security chips are overcoming modern scaling limits
How programmable RISC-V solutions optimize, control and direct custom accelerator functionality, unlocking the next generation of AI performance with SiFive intelligent control.
In a demonstration-only system, the companies showed the ability to run the modern Gemma4-E2B LLM model using ROCm 10.0 on SiFive servers powered by the SiFive Performance™ P870-D CPUs acting as the head node, and AMD Radeon™ AI PRO R9700 GPUs driving the inference offload.
The broader RISC-V standards process continues to deliver innovation that responds dynamically to evolving market needs. If you didn’t see the announcement, in an important milestone for the open hardware ecosystem, the RISC-V Board of Directors officially ratified the S-mode Physical Memory Protection (SPMP) version 1.0 specification on August 20, 2026.
Powered by SiFive’s latest RISC-V CPU technology, the new development platform enables hands-on software porting, workload tuning, and validation testing for hyperscaler customers and ecosystem partners
We’re thrilled to announce the launch of the SiFive Kernel Library or SKL (pronounced “skill”), an open-source collection of highly-optimized computational routines for the RISC-V Vector ISA (RVV) and its various extensions, including SiFive’s matrix engines.