Overview
The is a single-chip DVB-T, T2, C, S and S2 demodulator IP core extratced from production chip and silicon proven IP core. Its Operation is exclusive in that only one signal (standard) can be processed at any time. The DVB-T2 demodulator features microcontroller assisted operation enabling the fast tracking and response times demanded by the T2 standard. For the T, C, S and S2 standards, where the demands for immediate response are much lower, classical software control from the host processor has been implemented. Even though the silicon implementation is highly optimized, allowing each standard to share common hardware blocks, effort has been made to maintain a common look and feel with the established product line. Optimization of the T2 microcode requires additional compilers which are, for the moment, supported exclusively by T2M. The DVB T, T2 and C demodulators share a common input which may be operated in ZIF mode or in IF mode. Silicon as well as traditional CAN tuners are supported through a flexible IF/baseband interface with IF/BB AGC and I2C control. A separate input is implemented for the DVB-S and S2 demodulators.This is single-channel tuner range is fully supported. Furthermore, the flexible ZIF IQ inputs, RF AGC and I2C allow the use of third-party tuner solutions when required.
Learn more about Modulation Demodulation IP core
This paper focuses on how direct RF sampling architecture has proved to be a felicitous approach for RF data conversion. The progress in converter technology has made it possible to increase the sampling rates and support very large bandwidth and multiple operating RF bands.
Synopsys is now shipping support for Bluetooth® 5.4, the latest specification from the Bluetooth SIG (Special Interest Group). The enhancements in Bluetooth 5.4 will open additional markets and use cases. This is one of the many inflection points in the Bluetooth Low Energy market that will be discussed in this paper.
Carriers are now deploying 5G across the globe driven by the need to keep up with relentless mobile data growth. 5G New Radio (NR) operates at higher frequencies to increase bandwidth, but at the expense of range. There will therefore be a need for a much larger number of 5G RUs to provide the same coverage. The availability of cost-effective, reliable and open 5G radio units is therefore critical.
This paper presents the design and performance of a key RF circuit necessary for the realization of a reconfigurable, integrated RF front-end: a tunable frequency, selectable bandwidth, on-chip, “SAW replacement” filter. The on-die tunable filter presented here has a tunable center frequency up to 1 GHz, a selectable bandwidth up to 40 MHz, and an adjacent channel rejection down to 60 dB.
To meet the demands for the multi-band, multi-mode wireless standards in the current market, a highly integrated wireless receiver (RX) is desired. CMOS technology has become the technology of choice for the integrated receiver design.
An efficient IP reuse strategy relies on IP blocks with wide applicability. That makes generic blocks, such as programmable processors preferable. However, in many applications such as handheld wireless terminals, additional silicon area and power consumption compared to fixed function solutions can not be accepted.
