Vendor: Allegro DVT Category: CPU

Neural Video Processor IP

The NVP300, AI-based Neural Video Processing IP push video quality to the next level by leveraging the features and benefits of A…

Overview

The NVP300, AI-based Neural Video Processing IP push video quality to the next level by leveraging the advanced features and benefits of AI based video processing technologies.

The NVP300 IP features an optimized hardware implementation to deliver real-time AI processing of 4K video whithin best-in-class silicon area and power budget suitable for embedded products. It implements a range of AI-based algorithms to enhance the subjective quality of video and reduce noise to achieve better compression ratios.

Interfaces

  • AMBA APB Interface for control registers
  • AMBA AXI Interface for data access

Key features

  • Programmable Bithdepths (8, 10, 12-bit)
  • Programmable Chroma Subsampling Formats (4:2:0, 4:2:2, 4:4:4)
  • Optional Buil-in MCU
  • Supported Resolutions from HD30 up to 8K120
  • Wide range of optional Pre-Post Processing Features:
    • Color Space Conversion
    • Crop and Resize filters
    • Bithdepth and Chroma Subsampling format conversion

What’s Included?

  • RTL Source Code
  • C Control Software
  • Bit Accurate Reference Mode
  • Documentation

Specifications

Identity

Part Number
NVP300 Series
Vendor
Allegro DVT
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Allegro DVT
HQ: France

Learn more about CPU IP core

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Frequently asked questions about CPU IP cores

What is Neural Video Processor IP?

Neural Video Processor IP is a CPU IP core from Allegro DVT listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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