Vector-Capable Embedded RISC-V Processor

The EMSA5-GP is a highly-featured 32-bit RISC-V embedded processor IP core optimized for processing-demanding applications. It is equipped with floating-point and vector-processing units, cache memories, and is suitable for concurrent execution in a multi-processor environment.

It implements a five-stage pipeline, delivering single-cycle integer operations and efficient handling for floating-point and vector workloads. The core supports both RV32I and RV32E instruction sets and is configurable to support ISA extensions for Integer Multiplication/Division (M), Atomic Instructions (A), Single/Double-Precision Floating-Point (F/D), and Compressed Instructions (C). It further implements Physical Memory Protection (PMP), with up to 16 regions, to enable memory isolation and enhance the system’s safety and security.

The core’s RISC-V vector extension (RVV) subset enables vectorized processing on 32-bit vector elements—configurable for 64 (2 × 32-bit), 128 (4 × 32-bit), or 256 (8 × 32-bit) bits—supporting vector processing of 2, 4, or 8 lanes of 32-bit elements per instruction. The vector unit can accelerate DSP, AI, and bulk data compute tasks by supporting vector loads and stores, arithmetic operations, reductions, permutations, and scalar moves. The vector extension is accessed through dedicated CSRs and connects directly to the AMBA^® AHB-Lite external bus and unified L1 cache (up to 64KB, 4-way set associative), providing high-throughput memory access.

The EMSA5-GP core also includes an optional single or double precision FPU, configurable tightly-coupled memory (ITCM/DTCM) for deterministic memory access, a native AHB-Lite master interface, comprehensive debug and trace provisions (JTAG, RVFI, TIP), and programmable interrupt support.

Easy Integration and Low Risk

The processor core uses AMBA^® AHB-Lite, and low-latency Tightly Coupled Memory (TCM) interfaces for fetching instructions and accessing data and peripherals.

Part of the family of processor cores available from CAST for more than a decade and used by hundreds of customers, the EMSA5-GP IP core has been designed for easy reuse and integration, has been rigorously verified, and is LINT-clean, scan-ready, and silicon-proven. It is available in SystemVerilog source code.

To further accelerate development, the processor core can be delivered pre-integrated with bus infrastructure cores, typical microcontroller peripherals, memory controllers, and interconnect IP cores. Please contact CAST Sales for details.

Software Development

The EMSA5-GP can be used with RISC-V compatible toolchains, libraries, and IDEs such as those from IAR and Lauterbach.

Reference designs on FPGA development boards are available to ease evaluations and accelerate code development. Contact CAST Sales for more information.

Compact & Efficient Architecture

• Small silicon footprint for lower leakage and dynamic CPU power
  • From 100k gates
• Single-issue, in-order, 5-stage pipeline
• Harvard architecture with separate instruction and data TCMs and an optionally cached 32-bit AHB-Lite interface
• Optional instruction and data cache with synthesis-time configurable associativity and size

Performance

• 2.43 Coremarks/MHz
• Over 500 MHz in 16 nm

RISC-V Features

• 32-bit Base RISC-V ISA (RV32I/E) with Compressed Instructions (C), Multiply/Divide (M), Single/Double-Precision Floating-Point (F/D), Atomic Instructions (A), and Zifencei
• Supports User and Machine Modes
• Core Local Interrupt Controller (ACLINT) for timer and software interrupts
• Programmable Interrupt Controller (PLIC) for up to 16 interrupt targets and up to 1023 interrupt sources
• Physical Memory Protection with up to 16 regions
• Wait for Interrupt (WFI)

Available Pre-Integrated Platforms

• Integrate bus fabric with peripherals such as GPIO, UART, Real-Time Clock, Timers, I2C, and SPI
• Optionally customized to include memory controllers, interconnects, and more from the CAST IP line
• FuSa ISO 26262 ASIL-Ready Design available

Low Risk & Flexible Licensing

• Industry-standard licensing terms with royalty-free options
• Reliable vendor with an extensive track record and excellent support
  • Thousands of IP core licenses, and billions of units shipped with IP from CAST since 1997
  • Experienced and responsive support team with a 24/7 culture

Debug and IDE Support

• JTAG Debug with hardware triggers
• Compatible with RISC

• The core is available for ASICs in synthesizable Verilog.
• It includes everything required for successful implementation: extensive documentation, a testbench, a sample SoC design, and sample synthesis and simulation scripts.