Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Nuclei System Technology
Category:
CPU
32-Bit Automotive Processor - 9-Stage Pipeline, Dual-issue
NA900 series processor is the 1st ISO26262 ASIL-B/D Product Certified RISC-V CPU IP, Nuclei self-developed STL supports multiple …
Overview
NA900 series processor is the 1st ISO26262 ASIL-B/D Product Certified RISC-V CPU IP, Nuclei self-developed STL supports multiple ASIL-B automotive use cases.
NA900D Series
- Systematic Capability:ASIL D
- Hardware Safety Integrity: ASIL D in DCLS mode
NA900B Series
- Systematic Capability:ASIL D
- Hardware Safety Integrity: ASIL B
- Nuclei self developed Softwate Test Library for ASIL B application
- Fault Injection simulation FMEDA report for configurable design
- ASIL B support fot both split mode and singlecore mode
- Safety enhanced hardware for trade-off between diagnostic coverage and hardware cost
Key features
- RISC-V RV32 IMACFDPVBZfh ISA supported
- Dual Issue, in-order 9 stage Harvard Pipeline
- 64-bit AXI System Bus, Configurable 64-bit AXI slave port
- Double, Single and Half-Precision floating point
- Configurable SIMD DSP Extension
- Configurable Instruction and Data Cache
- Configurable ILM (Instruction Local Memory) with ECC
- Configurable DLM (Data Local Memory) with ECC
- PMP supported to meet the system security needs
- Full Standard Debug Function with JTAG and cJTAG Port
- Full Standard RISC-V Toolchain, and Linux\Windows IDE supported
Block Diagram
NA900 block diagram
Benefits
- Real-time Feature
- RV32IMACFDPB
- 9 Stage Pipeline Dual-issue
- I/D Cache
- Security(PMP, TEE)
- AXI System Bus
- RISC-V Standard Debug
- JTAG & cJTAG
- Low Latency Interrupt
- Full Dev Kit & SDK
Specifications
Identity
Part Number
NA900
Vendor
Nuclei System Technology
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
China
Learn more about CPU IP core
Announcing Arm AGI CPU: The silicon foundation for the agentic AI cloud era
For the first time in our more than 35-year history, Arm is delivering its own silicon products – extending the Arm Neoverse platform beyond IP and Arm Compute Subsystems (CSS) to give customers greater choice in how they deploy Arm compute – from building custom silicon to integrating platform-level solutions or deploying Arm-designed processors.
ChiPy®: Bridge Neural Networks and C++ on Silicon — Full Inference Pipelines with Zero CPU Round-Trips
The ChiPy DSL is Quadric's Python framework for building complete on-chip pipelines. Using YOLOX-M as a case study, we show how backbone inference, box decoding, and NMS run entirely on the Chimera GPNPU — no host CPU intervention, no DDR round-trips, just Python compiled to silicon.
Unleashing Leading On-Device AI Performance and Efficiency with New Arm C1 CPU Cluster
As part of the new Arm Lumex compute subsystem (CSS) platform, the Arm C1 CPU cluster – the first built on the Armv9.3 architecture – is the next evolution of our highest performing CPU cluster for consumer devices, designed to unleash the full potential of on-device AI and elevate the user experience.
Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection
Hardware fuzzing has recently gained momentum with many discovered bugs in open-source RISC-V CPU designs. Comparing the effectiveness of different hardware fuzzers, however, remains a challenge: each fuzzer optimizes for a different metric and is demonstrated on different CPU designs.
Introducing Cortex-A320: Ultra-efficient Armv9 CPU Optimized for IoT
Unlock ultra-efficient performance, advanced AI processing, and robust security with the Cortex-A320—designed to power the future of IoT and edge AI innovation.
Frequently asked questions about CPU IP cores
What is 32-Bit Automotive Processor - 9-Stage Pipeline, Dual-issue?
32-Bit Automotive Processor - 9-Stage Pipeline, Dual-issue is a CPU IP core from Nuclei System Technology listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.