The Synopsys ARC® VPX DSP Family is optimized for the unique power, performance and area (PPA) requirements of embedded workloads…
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Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
The Synopsys ARC® VPX DSP Family is optimized for the unique power, performance and area (PPA) requirements of embedded workloads…
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer.
The Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
In Digital video broadcasting for digital transmission for satellite applications, a FEC (Forward Error Correction) sub-system is…
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
In Digital video broadcasting for terrestrial broadcasting systems, a FEC sub-system is needed.
Half precision, IEEE 754, floating point fused multiply add
The eSi-HP-FP-Fused-Multiply-Add IP core implements half-precision (16-bit), IEEE 754 compliant, floating-point fused multiply an…
Single precision, IEEE 754, floating point to integer conversion
The eSi-SP-FP-Float-to-Int IP core implements single-precision (32-bit), IEEE 754 floating-point to integer conversion.
Single precision, IEEE 754, floating point square root
The eSi-SP-FP-Square-Root IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point square root operations.
Single precision, IEEE 754, floating point divider
The eSi-SP-FP-Divider IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point division.
Single precision, IEEE 754, floating point multiplier
The eSi-SP-FP-Multiplier IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point multiplication.
Single precision, IEEE 754, floating point adder
The eSi-SP-FP-Adder IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point addition and subtraction ope…
Digital FIR filter with APB interface
The eSi-FIR core provides an interface to filter and decimate time interleaved multi-channel data.
32-channel 64-QAM/256-QAM J.83 Annex B Cable Modulator
The IPrium-J83B-C-Modulator IP Core is 32-channel J.83B Modualtor with MAX5861 (MAX5862) support.
Fast Fourier Transformation (FFT) calculation IP block.
Library of mathematical and floating point (FP) components
Optimized for efficient hardware implementation, the Synopsys Foundation Cores include a library of mathematical and floating poi…
DVB-S2X-LDPC Decoder
LDPC codec for NAND FLASH error correction
The LDPC IP is aLow-densityparity-check code encoder and decoder designed for 3D NAND Flash error correction to address the relia…
AI and DSP performance leader with up to 4X the NN performance and 2X the DSP performance of the HiFi 4 DSP, ideal for digital as…