ISDB-S3-LDPC-BCH Decoder
- Channel Coding
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
ISDB-S3-LDPC-BCH Decoder
The designed Single Carrier is working at adjustable sampling rate as low as 83.457 KHz, as high as 56 MHz It supports adjustable…
Adaptive Interactive detection- Per-Survivor Processing
1: CPM Modulator/ Demodulator Data Rate 200kbps to 10 Mbps in steps of 100Kbps Modulation Index Programmable up to 0.5 Baseband F…
In Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
Tensilica DSP IP supports efficient AI/ML processing
The Cadence AI IP platform includes the extensible DSP platform from Cadence, which provides flexible instruction sets designed t…
The designed Single Carrier is working at adjustable sampling rate as low as 83.457 KHz, as high as 56 MHz and it supports adjust…
LTE/NR Small Block Lengths Decoder
TC5390 is a decoder IP Core compliant with the small block lengths coding scheme for UCI as defined by 3GPP 4G-LTE and 5G-NR spec…
Tensilica FloatingPoint KQ7/KQ8 DSPs
Super-high-performance DSPs specifically optimized for floating-point workload with exceptional PPA Cadence® Tensilica® FloatingP…
Tensilica FloatingPoint KP1/KP6 DSPs
High-performance DSPs designed for floating-point-centric processing with ultra-low energy and small area Cadence® Tensilica® Flo…
2X the performance of the HiFi 3 DSP for DSP-intensive applications like multi-channel, digital assistant front-end processing, a…
DVB-T2 Demodulator and LDPC/ BCH Decoder
The demodulator is designed to be used together with an RF tuner, and an analog to digital converter.
ZSP5000H is a programmable Vector Digital Signal Processor Core targeted for high performance Computer Vision and Image processin…
ZSP5000UL is a programmable Vector Digital Signal Processor Core for high performance computer vision and image processing applic…
ZSP5000 is a programmable Vector Digital Signal Processor Core for high performance computer vision and image processing applicat…
ZSPNano+ is a small, energy efficient, Digital Signal Processor Core for high performance Voice/Audio/Wireless applications.
CCSDS AR4JA LDPC Encoder and Decoder with code rates 1/2, 2/3, 4/5 and block sizes 1K, 4K, 16K
The IPrium-LDPC-CCSDS-AR4JA-Encoder-Decoder IP Core implements Low Density Parity Check (LDPC) forward error correction algorithm…
IEEE 802.11n/ac/ax Encoder and Decoder
The IPrium-LDPC-802.11-WIFI-Encoder-Decoder IP Core implements Low Density Parity Check (LDPC) forward error correction algorithm…
CCSDS 131.2 SCCC Turbo Encoder and 64-APSK Modulator
The IPrium-CCSDS-SCCC-Modulator-Encoder IP Core implements the CCSDS modulation standard 131.2-B.
CCSDS SCCC Modulator/ Turbo Encoder
CCSDS SCCC Modulator/ Turbo Encoder
DVB-RCS2 Turbo Decoder and Encoder
On the transmitter side, the turbo-phi encoder architecture is based on a parallel concatenation of two double-binary Recursive S…