The BCH design includes two independent units, an encoder for generation of the BCH code, and decoder for the BCH code decoding.
- Channel Coding
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
The BCH design includes two independent units, an encoder for generation of the BCH code, and decoder for the BCH code decoding.
Dolby Digital/AC-3/MPEG Audio Decoding Core
The J1 is a core cell design of an application specific signal processor which performs both Dolby Digital/AC-3 and MPEG audio de…
High Speed CCSDS Turbo Decoder with Optional Viterbi Decoder
This is a CCSDS compatible 16 state error control turbo decoder.
The CMS0009 DVB-T/DVB-H Modulator provides all the necessary processing steps to modulate a single (or pair of hierarchical) tran…
IEEE 802.16 WirelessMAN OFDM Channel Codec
The CMS0005 802.16 Channel Codec provides all of the functionality necessary to implement the back end data processing in an 802.…
High Speed Inmarsat Compatible Turbo Decoder
This is an Inmarsat compatible 16 state error control turbo decoder.
The CMS0002 Viterbi Decoder core implements Viterbi’s algorithm for maximum likelihood decoding of non-feedback convolutional cod…
The CMS0010 DVB-S/-DSNG Modulator with integrated Reed-Solomon encoder has been designed specifically to address the requirements…
The VA08V is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
softDSP released 3GPP compliant Turbo decoder IP core in May, 2000.
3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible 3GPP (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) error control decoder.
3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO 8 state turbo encoder
This is a high speed 8 state 3GPP™ (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) compatible paralle…
Very High Speed 8 State MAP Decoder
This is a very high speed 8 state maximum a posteriori (MAP) soft-in-soft-out (SISO) triple interleaved error control decoder wit…
Enabling Next-Generation Voice AI and Immersive Audio Applications With the rise of immersive audio and AI in home entertainment,…
Parameterizable compact BCH codec
The core targets the lower-performance error correction applications using Bose–Chaudhuri–Hocquenghem codes (BCH codes) that prio…
20-bit -120dB THD+N Multi-Channel Audio Sample Rate Converter
The ASRC-premier (CWda54) is part of Coreworks family of multi-channel Asynchronous Audio Sample Rate Converter (ASRC).
The CORDIC IP provides hardware acceleration of mathematical functions (mainly trigonometric ones) commonly used in motor control…
The Fast Fourier Transforms (FFT) are an efficient class of algorithms for digital computation of the Discrete Fourier Transform …
CRC (Cyclic Redundancy Check) Calculation Unit
CRC (Cyclic Redundancy Check) calculation unit using a polynomial generator from 8-bit/16-bit/32-bit data words CRC code.
Double & Single Precision IEEE-754 complete FPU
The A2FD is a fully synthesizable module implemented in Verilog RTL.