Error Correcting Code for SRAMs
The ECC-SRAM core adds protection against SRAM data corruption.
- Channel Coding
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
Error Correcting Code for SRAMs
The ECC-SRAM core adds protection against SRAM data corruption.
512-bit Vector DSP IP, Single Core with Functional Safety
The ASIL B and C compliant ARC® VPXxFS DSP IP is a family of VLIW/SIMD processors enabling automotive system-on-chip (SoC) design…
512-bit Vector DSP IP, Quad Core with Functional Safety
The ASIL B and C compliant ARC® VPXxFS DSP IP is a family of VLIW/SIMD processors enabling automotive system-on-chip (SoC) design…
512-bit Vector DSP IP, Dual Core with Functional Safety
The ASIL B and C compliant ARC® VPXxFS DSP IP is a family of VLIW/SIMD processors enabling automotive system-on-chip (SoC) design…
512-bit Vector DSP IP, Single Core
The ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on…
512-bit Vector DSP IP, Quad Core
The ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on…
512-bit Vector DSP IP, Dual Core
The ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on…
256-bit Vector DSP IP, Single Core with Functional Safety
The ASIL B and C compliant ARC® VPXxFS DSP IP is a family of VLIW/SIMD processors enabling automotive system-on-chip (SoC) design…
256-bit Vector DSP IP, Single Core
The ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on…
256-bit Vector DSP IP, Dual Core with Functional Safety
The ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on…
256-bit Vector DSP IP, Dual Core
The ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on…
128-bit Vector DSP IP, Single Core with Functional Safety
The ASIL B and C compliant ARC® VPXxFS DSP IP is a family of VLIW/SIMD processors enabling automotive system-on-chip (SoC) design…
128-bit Vector DSP IP, Single Core
The ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on…
128-bit Vector DSP IP, Dual Core with Functional Safety
The ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on…
128-bit Vector DSP IP, Dual Core
The ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on…
Scalar and SIMD floating point option for the ARC HS5x, HS5xD and HS6x processors
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
The FastMath Pack is a math processing accelerator for the ARC HS family
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
BCH Encoder and Decoder IP Core
The IP Core implements BCH Code encoding and decoding.
optimized for generative AI applications running Transformer based NN models that enables efficient and simple system designs.
4x improvement to vector computation with 4x sustained bandwidth of prior generations
Building on the popular SiFive Intelligence™ X280 products’ success in AI/ML applications across mobile, infrastructure and autom…