Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
Medium throughput, compact Reed Solomon decoder
This implementation of a M=8 Reed Solomon decoder has been designed to use a minimum set of resources whilst maintaining a medium…
TETRA-TEDS Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible TETRA-TEDS error control decoder.
Behavioral knowledge space combination rule core with parallel operation
So_ip_ecr_bks_p core can be used to implement the Behavior Knowledge Space (BKS) combination rule to calculate the ensemble class…
Behavioral knowledge space combination rule core with serial operation
So_ip_ecr_bks_s core can be used to implement the Behavior Knowledge Space (BKS) combination rule to calculate the ensemble class…
Weighted majority voting combination rule core with parallel operation
So_ip_ecr_mvt_p core can be used to implement the Weighted Majority Voting combination rule to calculate the ensemble classificat…
Majority voting combination rule core with parallel operation
So_ip_ecr_mv_p core can be used to implement several Majority Voting combination rules to calculate the ensemble classification o…
Majority voting combination rule core with serial operation
So_ip_ecr_mv_s core can be used to implement the several variants of the Majority Voting combination rule to calculate the ensemb…
Very High Speed 3GPP LTE Turbo Decoder
This is a very high speed and fully compatible 3GPP LTE turbo decoder with one, two, four or eight parallel MAP decoders.
Very High Speed 3GPP LTE Turbo Encoder
This is a very high speed 8 state 3GPP LTE compatible parallel concatenated turbo encoder.
High Speed CCSDS Turbo Encoder
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder.
Viterbi decoder for 3GPP WCDMA and 3GPP-LTE
TC2000 is a flexible Viterbi decoder covering LTE, 3GPP WCDMA and WiMAX 16e/m specifications.
High Throughput Reed Solomon Decoder
This is a Reed Solomon decoder capable of operating with shortened codewords.
1KB/ECC96 NAND Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
The Zaltys ISDBT-M IP core is a 3-layer ISDB-T hierarchical modulator compatible with the ARIB STD-B31 standard for Terrestrial I…
Fully Configurable Radix 2 FFT/IFFT Processor
ntFFT core is a fully configurable solution that performs the FFT and IFFT transform.
ITU-Ghn LDPC Encoder / Decoder
TC4400 is a LDPC decoder core that is fully compliant with ITU G.hn (wireline home networking) specifications.
512B/ECC16 Nand Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
High-performance Low-memory Mixed Radix FFT
This FFT is an efficient implementation of the Decimation in Frequency (DIF) Cooley-Tukey FFT.
1KB/ECC40 NAND Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
High Performance DTMB (GB20600-2006) Demodulator Core
Digital demodulator fully supporting GB20600-2006 China DTV standard.