In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.
- Channel Coding
- Mature
- Now
- 3GPP LTE
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.
In the downlink transmission, the physical downlink shared channel (PDSCH) carries the user data (Transport block).
In Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
TC1720 is a high throughput and low latency Viterbi decoder optimized for WiFi and LTE applications.
TC5100 is a flexible LDPC encoder/decoder Core.
The MVD ISDB-T core is a drop-in module that includes the following functions : • Input data framer from DVB-SPI source (MPEG-TS …
Reconfigurable Parallel CRC Generator
Parallel CRC IP is reconfigurable high-speed CRC generator, flexible in terms of input data width and generating polynomial.
Multi Function Viterbi Decoder
The VA08VA is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 80…
8-Channel PCM-to-PWM Modulator in Fujitsu 55nm
The AR35F01A is a digitally coded conversion IP that translates 8-ch (4 stereo channels) of 16-24bit pulse-code modulated (PCM) i…
The eSi-QRD-LSL is a QR-Decomposition Least Squares Lattice (QRD-LSL) core is a high throughput IP core that finds application in…
A efficient pipelined radix-2 squared FFT.
Configurable Turbo Product Codec
In channel coding redundancy is inserted in the transmitted information bit-stream.
LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encodi…
Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
In Digital video broadcasting for terrestrial broadcasting systems, a FEC sub-system is needed.
The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer.
Maximum normalised correlation core
The eSi-MNC core provides the control and data plane interfaces to a Maximum Normalised Correlation module.
This is a high throughput QAM constellation demapper and Log Likelihood Ratio (LLR) bit-metric generator.