High-speed clock receiver operating up to 2.5 GHz with low output jitter
The ODT-CRX-2P5G-16FFCT is a high-speed clock receiver circuit capable of operating up to 2.5 GHz with low output jitter.
- Clock Generator
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
High-speed clock receiver operating up to 2.5 GHz with low output jitter
The ODT-CRX-2P5G-16FFCT is a high-speed clock receiver circuit capable of operating up to 2.5 GHz with low output jitter.
Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
The ODT-ADS-7B64G-3 is an ultra-high-bandwidth time-interleaved ADC designed in a 3nm CMOS process.
The ODT-ADS-12B9G-16 is an ultra-highperformance time-interleaved ADC designed in a 16nm CMOS process.
39GHz High-Efficiency CMOS Power Amplifier for 5G mmWave Applications
The FCM3901 is a high-efficiency 39GHz power amplifier developed for 5G mmWave applications.
Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
The Wi-Fi 7 (802.11be) RF transceiver IP, operating in 2.4GHz / 5GHz / 6GHz bands, is tailored for next-generation high-performan…
Ku-Band Phased Array Tx-FE in TSMC 180nm RF
The TRV801TSM180RF IP is a Ku-Band (14GHz to 14.5GHz) Transmitter (Tx) in TSMC 180nm RF CMOS process technology.
Ku-Band Phased Array Rx-FE in TSMC 180nm RF
The TRV501TSM180RF IP is a Ku-Band (10.7GHz to 12.75GHz) Receiver (Rx) RFFE TSMC 180nm RF CMOS process technology.
8 Bit 6 GS/s Current Steering DAC on Fujitsu 55 nm CS250L
The IP consists of an 8 bit current steering DAC clocked externally for 4 - 6 GS/s.
7 Bit 6 GS/s Folding ADC on Fujitsu 55 nm CS250L
The IP consists of a 7 bit monolithic folding ADC clocked externally for 6 GS/s.
ULP Clock Generator - GLOBALFOUNDRIES 22FDX
ABB-enabled, All-Digital PLL clock generator for ultra-low power clocking in energy efficient Systems on Chip.
Current Output 12 Bit 250 MSPS DAC on 16nm
The ODT-DAC-12B9G-16 is a high-performance current steering 12-bit DAC that operates at an update rate of up to 9GSPS.
Power and Clock Generation IP - GLOBALFOUNDRIES® 22FDX®
Tightly integrated power management platform with a soft-IP wrapper around Analog / Mixed-Signal hard macros which generate all s…
UHF Passive RFID Front-End - EPCGlobal Class 1 Gen 2/ISO18000-6C Compliant
This macro-cell is an ultra low power analog/RF front-end core designed for SilTerra 0.18μm CMOS technology.
Power-On Reset - Flexible Threshold (1-1.3V), Ultra Low Current (100nA) - SilTerra 0.16µm CL160G
This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.16μm CL160G CMOS technology.
General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
This Integer-N Hybrid (Digitally Aided Analog) PLL generates clock signals within broad frequency range.
500nm Trimmed Low Power Bandgap
The BG102 is a 1.2V CMOS low power, medium precision CMOS bandgap cell designed for use in a wide variety of mixed signal device …
Auxiliary DAC - 12-bit Successive Approximation Register (SAR) DAC
This digital-to-analog converter implements segmented R-2R and thermometer decoder architecture to achieve 12-bit resolution.
HCLTech offers a low drop-out (LDO) voltage regulator that has been designed in a 40nm GF technology.
12-bit, 8 GSPS High Performance DAC in 16nm CMOS
The ODT-DAC-12B8G-16 is a highperformance current steering 12-bit DAC that operates at an update rate of up to 8GSPS.
12-bit, 8 GSPS High Performance ADC in 16nm CMOS
The ODT-ADS-12B8G-16 is an ultra highperformance time-interleaved ADC designed in a 16nm CMOS process.