Power and Clock Generation IP - GLOBALFOUNDRIES® 22FDX®

Tightly integrated power management platform with a soft-IP wrapper around Analog / Mixed-Signal hard macros which generate all supply voltages and clock signals needed to run highly efficient SoCs in GlobalFoundries® 22FDX®. Running from only one supply voltage and reference clock, the IP generates its own internal supplies and references, and those needed to run the Racyics® ABX® Generator. With a simple digital interface, and a comprehensive register file for configuration, the IP simplifies chip power management and can be customized to a wide range of applications.

IP SPECIFICATION

•  Supply and Reference Voltages
  • 0.8 V supplies for always-on logic and a     power-shutoff domain
  • Seamless switching between LDO and DC / DC      converter for fast startup and high efficiency
  • Variable 0.4 to 0.9 V supply for additional power      domains supporting up to 250 mA load current
  • 0.6 V voltage reference for MRAM
•  Clock Generation
  • Ultra-low power 50 MHz clock generator
  • Variable-frequency PLL clock generator with a      wide frequency range reaching up to 500 MHz
•  Control Logic
  • Simple handshake protocol for selecting IP     operation modes with different power and     clock generation settings
  • APB interface and explicit inputs for detailed     configuration of each sub-block
  • Reference clock failure detection and handling     for safe shutdown of high-current circuits

• APL views for EMIR analysis
• Datasheet with integration guidelines
• GDSII layout
• LEF abstract
• .lib / .db timing
• LVS netlist
• Verilog simulation models
• Synthesizable controller RTL with implementation constraints