Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm

The ODT-ADS-7B64G-3 is an ultra-high-bandwidth time-interleaved ADC designed in a 3nm CMOS process.

This 7-bit, 64GSPS ADC supports ac-coupled input signals up to Nyquist and features a full-scale range of 0.45Vpp differential, excellent dynamic performance, and low noise operation.

The ADC architecture is optimized to maximize performance while minimizing power and area consumption. The ac-coupled RF input is internally buffered and sampled and then distributed efficiently to time-interleaved ADC channels.

The ADC includes built in calibration to remove time interleaving artifacts, including offset mismatch, gain mismatch and timing skew. It also includes internal analog test probes to enable measurement of DC signals.

To maximize SNR, the ADC includes an ultra-low-jitter clock distribution network.

• Ultra-high bandwidth time-interleaved ADC
• 7-bit ADC resolution
• Sampling rate up to 64GSPS
• Fully differential operation
• 0.45Vpp differential input signal range
• Fully specified from -40 C to 125 C
• Internal calibration circuitry to correct timeinterleaving errors.
• Power dissipation scalable with sampling rate

• General purpose software defined radioHigh speed data acquisition systems
• Cellular base station
• Broadband communications
• Wideband satellite receiver
• Optical communications

• Datasheet
• Hard Macro (GDSII and CDL)
• Characterization Report
• Spectre Netlist (as needed)
• Verilog Behavioral & Netlist Model
• Timing Wrapper & Model
• Power Spreadsheet
• Physical Abstract (LEF, milkyway)
• Device Accurate IO Model
• Integration and Customer Support