40G Ethernet MAC and PHY FPGA IP Core
The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010.
- Single-Protocol PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
40G Ethernet MAC and PHY FPGA IP Core
The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010.
This IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium.
1G/10Gb Ethernet PHY Intel® FPGA IP
The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding s…
Multi-Rate Ethernet PHY FPGA IP
The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device re…
The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection.
As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the Warp Intel® FPGA IP provides a optimized solution fo…
Video and Vision Processing Suite
The Intel® FPGA Video and Vision Processing Suite is a collection of next-generation Intel® FPGA intellectual property (IP) funct…
Forward-error correction (FEC) channel codes commonly improve the energy efficiency of wireless communication systems.
Tone Mapping Operator (TMO) Intel® FPGA IP
As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the Tone Mapping Operator (TMO) Intel® FPGA IP corrects …
A numerically controlled oscillator (NCO) is a digital signal generator, which synthesizes a discrete-time, discrete-valued repre…
The CIC Intel FPGA IP core implements a Cascaded integrator-comb (CIC) filter with data ports that are compatible with the Avalon…
The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with t…
Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy…
Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
PQCryptoLib-Embedded is a versatile, CAVP-ready cryptography library designed and optimized for embedded devices.
xSPI Multiple Bus Memory Controller
The industry ‘defacto standard’ memory controller for xSPI-like memories: HyperBus™ 1.0, 2.0 and 3.0 – OctaBus™ – Xccela® Bus – O…
Filtering with packet payload scanning Message filters are placed in the middle of a TCP / TLS session to scan application data, …
Secure protocol communication by hardware Our SSL/TLS engine accelerates and offloads processing for encryption / decryption and …
Full hardware TCP/UDP protocol stack realize both high performance and guaranteed delivery Our TCP/UDP offload engine supports si…
OFDM - Orthogonal Frequency Division Multiplexing
OFDM - Orthogonal Frequency Division Multiplexing
PCIe Gen 6 controller IP