Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Intel® Precision Time Protocol Servo (Intel® PTP Servo) FPGA IP
Coordinate the actions of disparate electronic systems that must be synchronized in time with Intel® PTP Servo, which employs har…
Scalable Switch Intel® FPGA IP for PCI Express
The Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream…
Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller I…
The F-Tile Intel® Hard IP supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL…
Intel® Arria® 10 and Intel® Cyclone® 10 PCIe Hard IP
Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is complia…
The Extensible Radio Access Network (O-RAN WG4 Fronthaul Interface) defines a fronthaul interface between a lower-layer split dis…
Multichannel DMA Intel FPGA IP for PCI Express*
The Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility to support various applica…
The MACsec Intel® FPGA IP core implements the IEEE Media Access Control Security standard as defined in 802.1AE (2018) as fully c…
Low Latency Ethernet 10G MAC FPGA IP
The Low Latency Ethernet 10G MAC FPGA IP core (soft IP) offers low round-trip latency, and an efficient resource footprint.
Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core
Intel® offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet Intel® FPGA IP core targe…
The JEDEC committee created the JESD204 data converter serial interface standard to standardize and reduce the number of data inp…
The Interlaken Intel® FPGA IP core is Interlaken Protocol Definition v1.2 compliant and allows system developers to achieve high …
Interlaken Look-Aside Intel® FPGA IP
Interlaken Look-Aside is a scalable protocol that allows interoperability between a datapath device and a look-aside coprocessor …
The enhanced Common Public Radio Interface (eCPRI) Altera® FPGA IP core implements the eCPRI specification version 2.0.
Compute Express Link (CXL) FPGA IP
Industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.
The Common Public Radio Interface (CPRI) Altera® FPGA IP core implements the CPRI Specification V7.0.
Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core
The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instant…
Intel® Agilex™ 7 F-Tile Ethernet Hard IP
The Intel® Agilex™ 7 FPGA F-Tile incorporates a fracturable, configurable, hardened Ethernet protocol stack for supporting rates …
Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile Hard IP
The Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible …
The 50G Ethernet Intel® FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Cons…