“LucidEye” improves the visibility of unclear images such as those deteriorated due to weather conditions (snow, haze, or fog), a…
- Video Processing
- H.264 (ISO/IEC 14496 - 10)
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
“LucidEye” improves the visibility of unclear images such as those deteriorated due to weather conditions (snow, haze, or fog), a…
Dual-core video codec- AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Dual-core video codec- AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Ultra Low-Power High-Performance AFE in 12nm
The ODT-AFE-1T1R-12 is an ultra-high-performance AFE designed in a 12nm process.
Ultra Low-Power High-Performance AFE on 12nm
The ODT-AFE-4T4R-12nm is an ultra-high-performance AFE designed in a 12nm CMOS process.
High-performance reference current and voltage generator in 12nm CMOS
The ODT-REF-SV1P8-12nm is a highperformance reference current and voltage generator.
Ultra-Low-Power Process, Voltage, and Temperature Monitor in 3nm
The ODT-PVT-ULP-001C-3nm is an ultra-low power temperature, voltage and process monitor designed in a 3nm CMOS process.
Ultra-Low-Power Process/Voltage/Temperature Monitor in 12nm
The ODT-PVT-ULP-001C-12nm is an ultra-low power temperature, voltage and process monitor designed in a 12nm CMOS process.
The MIPI RFFE Master controller IP is a optimized and technology agnostic implementation of the MIPI RFFE v.3.1 standard targetin…
Hash and HMAC Functions Accelerator
The DSHA2-384 - a universal solution that accelerates SHA2-384 hash with HMAC mode.
Spatial Audio & Head Tracking Solution
Ceva-RealSpace is a Spatial Audio software solution combining precise 3D rendering and accurate, low-latency head tracking.
3.3 - 4.2V to -3.7V step-down DC/DC converter
180XFAB_DCDC_05 is capable to generate -4.2V ÷ -3.3V (-3.7V typical value) voltage and can maintain 50uA load for -3.7V output.
14-bit 1-channel 40 to 160 MSPS pipeline ADC
065STM_ADC_01 is a high-speed 1-channel 14-bit ADC based on a pipelined architecture.
USB 2.0 PHY IP, Silicon Proven in TSMC 16FFC
The entire physical layer (PHY) IP solution for USB 2.0 was created to provide exceptional performance and consume little power.
Vision DSP built using 128-bit SIMD and offering up to 0.4 TOPS of performance
Built using 1024-bit SIMD and offering up to 3.84TOPS of performance The Cadence® Tensilica® Vision Q8 DSP delivers up to 3.84 te…
Cache-Coherent HiFi 5s Symmetric Multiprocessor
Efficient 32-bit processing for audio enhancement algorithms, wideband voice codecs, and multi-channel audio The Cadence® Tensili…
High-performance, low-latency PHY for D2D connectivity
ULL TCP/IP, UDP/IP Offload Engine
High-performance TCP and UDP IP offload engine cores offer a reliable, ultra-low-latency solution for financial and network appli…
PUSCH Equalizer for 3GPP 5G NR
3GPP compliant equalisation, double uplink performance and spectral efficiency with this 5G NR Uplink Physical Shared Channel sol…
Secure Hash Algorithm-3 (SHA-3)
CYB- SHA3 implements Secure Hash Algorithm-3 (SHA-3) family of functions on binary data with the NIST FIPS 202 Standard.
Run-time Reconfigurable Neural Network IP
The Dynamic Neural Accelerator II (DNA-II) is a -efficient and neural network IP core that can be paired with any host processor.