The VESA DSC and VDC-M IP cores deliver visually lossless video compression for mobile, AR/VR and automotive display applications.
- VESA DSC
- VESA DSC 1.2b
Multimedia Interface IP cores provide the high-speed connectivity technologies required to transport video, audio, image, and display data across modern SoCs, ASICs, and electronic systems. These interfaces are essential for enabling seamless communication between processors, cameras, displays, sensors, and multimedia subsystems.
This category includes HDMI, DisplayPort, MIPI, V-By-One, and VESA DSC (Display Stream Compression) IP solutions. Available implementations may include controllers, PHYs, protocol stacks, bridge solutions, and complete subsystem IP supporting high-resolution displays, camera interfaces, video transport, display compression, and multimedia data exchange.
Compare multimedia interface IP cores by protocol standard, feature set, implementation model, and vendor offering to support your video, display, and media connectivity roadmap.
The VESA DSC and VDC-M IP cores deliver visually lossless video compression for mobile, AR/VR and automotive display applications.
The VESA DSC and VDC-M IP cores deliver visually lossless video compression for mobile, AR/VR and automotive display applications.
CSI-2 transmitter controller for application processor
LCD/HDMI Video Output Interface
LCD/HDMI Video output Interface supports various display modes and programmable display sizes.
MIPI CSI2 v1.3 Transmit Controller
The Veriest Solutions MIPI CSI-2 v1.3 Transmit Controller facilitates transmission over a standard high-speed unidirectional seri…
MIPI DSI-2 Transmitter v1.1 Controller IP, Compatible with MIPI D-PHY & C-PHY
MIPI is the Mobile Industry Processor Interface that provides specification for software and hardware interfaces in mobile termin…
The Veriest Solutions MIPI CSI-2 v1.1 Transmit Controller facilitates transmission over a standard high-speed unidirectional seri…
The V-by-One VIP is fully compliant with the V-by-One standard. Supports THine V-by-One HS, HS Plus
The eDP 2.0 Verification IP provides an effective & efficient way to verify the components interfacing with the eDP interface of …
The LLI Controller connects two chips together to create a single “virtual chip”, with both chips sharing the same memory.
To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to de…
The DSI Tx Controller IP is designed to provide MIPI DSI 1.3 – compliant high-speed serial connectivity for the host (mobile appl…
The DSI v1.3 Receiver Controller IP is designed to provide MIPI DSI 1.3 compliant high-speed serial connectivity for device (mobi…
MIPI DSI-2 Transmitter Controller IP Core
The MIPI Display Serial Interface (DSI-2) Transmitter (host processor interface) Controller IP provides a high-speed serial inter…
MIPI DSI-2 Receiver IP Controller Core
The MIPI Display Serial Interface (DSI-2) Receiver (display panel interface) Controller IP provides a high-speed serial interface…
Arasan Chip Systems is a SOC IP provider of a suite of MIPI compliant IP solutions, which consist of IP cores, verification IP, s…
Embrace the future of digital media with the VESA VDC-M v1.2 Encoder IP core.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
Arasan Chip Systems is a SOC IP provider of a suite of MIPI compliant IP solutions, which consist of IP cores, verification IP, s…