What is MIPI CSI2 Transmit Controller?
MIPI CSI2 Transmit Controller is a MIPI IP core from Veriest Solutions Ltd. listed on Semi IP Hub.
Vendor:
Veriest Solutions Ltd.
Category:
MIPI
MIPI CSI2 Transmit Controller
The Veriest Solutions MIPI CSI-2 v1.1 Transmit Controller facilitates transmission over a standard high-speed unidirectional seri…
Overview
The Veriest Solutions MIPI CSI-2 v1.1 Transmit Controller facilitates transmission over a standard high-speed unidirectional serial interface between CSI-2 Transmitter and Receiver. The receiver is typically a host image processor. The transmitter is typically part of a camera device supplying image data. The DPHY is the physical layer block to which the MIPI CSI-2 Transmit controller interfaces for transmission.
The CSI-2 Transmitter receives pixels by way of the ISP Interface or packed data by way of the PDI Interface. The CSI-2 Transmit Controller converts pixels into a byte stream, calculates and appends an ECC value to a short packet or to the header of a long packet. Packets are buffered in a FIFO and synchronized to the High-Speed Byte clock domain and sent to one or more of D-PHY lanes depending upon the lane distribution scheme set by the camera sensor.
The CSI-2 Transmitter receives pixels by way of the ISP Interface or packed data by way of the PDI Interface. The CSI-2 Transmit Controller converts pixels into a byte stream, calculates and appends an ECC value to a short packet or to the header of a long packet. Packets are buffered in a FIFO and synchronized to the High-Speed Byte clock domain and sent to one or more of D-PHY lanes depending upon the lane distribution scheme set by the camera sensor.
Key features
- Camera Serial Interface (CSI-2) version 1.1
- D-PHY version 1.1
- CSI-2 interface on device side supports
- Connectivity to D-PHY through PHY Protocol Interface (PPI) Interface
- Configurable up to 4 data lanes
- Maximum data rate of up to 1.5 Gbps per data lane
- Data synchronization from core clock domain to TxByteClkHS domain
- Support for Ultra Low Power Mode
- AMBA APB Slave for Control and Status
- CSI2 Protocol Layer supports
- All primary and secondary CSI-2 data formats
- Short and Long packet formats
- Check-Sum (CRC) Generation
- Error Correction Code (ECC) Generation
- Up to 4 image streams using virtual channels
- Data Type and Virtual Channel Interleaving
- External ISP interface supports
- Pixel Based User Interface (single, double, quad pixel wide)
- RAW and YUV formats
- Pixels to Byte Packing
- Packed Data Interface (PDI) supports
- 32-bit Packed Data (recommended memory storage format)
- Generic or user-defined byte-based data types
- Test interface for general purpose configuration of D-PHY
- Compatible with Synopsys DPHY
Block Diagram
VV1300 block diagram
Benefits
- Low Gate Count
- Low Power Consumption
- Fully Verified in with Advanced Function Verification
- Spyglass Lint Validated
- Standards Compliant
Applications
- MIPI CSI2 Compliant Camera Sensor
What’s Included?
- Synthesizable Verilog RTL
- Verilog test bench and test cases
- System Verilog verification environment and test cases
- Detailed block diagram and technical documents
Specifications
Identity
Part Number
VV1300
Vendor
Veriest Solutions Ltd.
Type
Silicon IP
Provider
HQ:
Israel
Frequently asked questions about MIPI IP cores
How should engineers evaluate this MIPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.