Vendor: Arasan Chip Systems Inc. Category: MIPI

DSI v1.3 Transmit IP Core

The DSI Tx Controller IP is designed to provide MIPI DSI 1.3 – compliant high-speed serial connectivity for the host (mobile appl…

Contact Provider Request Datasheet

Overview

The DSI Tx Controller IP is designed to provide MIPI DSI 1.3 – compliant high-speed serial connectivity for the host (mobile application processor) using 1 to 4 D-PHYs depending on bandwidth needs. Serial connectivity to the display module’s DSI device is implemented using 1 to 4 D-PHY’s (also available from Arasan), depending on display bandwidth needs. This IP connects to the D-PHYs through the PPI interface.

On the application processor side, Arasan’s DSI Host Controller provides the choice of DPI or DBI Interface to a graphics controller. A DBI interface provides downstream support of Types 1 to 3 display modules, and the DPI Interface is needed for Types 2 to 4 displays.

Initial configuration of Arasan’s MIPI DSI Host Controller can be done through programmed IO over the AHB bus, however, other bus interfaces can be provided upon request.

Key features

Compliant with the following MIPI specifications

  • Display Serial Interface (DSI) version 1.3.1
  • Display Pixel Interface (DPI-2) version 2.00
  • Display Bus Interface (DBI) version 2.00
  • Display Command Set (DCS) version 1.3
  • D-PHY version 1.2

DSI TX (Processor Host) interface supports

  • Connectivity to D-PHY through PPI Interface
  • 1 to 4 data lane support
  • Hi-Speed (HS) transmit from 80 Mbps to 2.5Gbps per lane
  • Low Power (LP) receive/transmit from/to device at 10 Mbps
  • Continuous and stoppable clocks on clock lane
  • Bus turnaround with contention and fault recovery
  • Switching to and from Low Power (LP) and Ultra-low Power (ULPS) modes
  • EOT enable/disable mechanisms
  • Multiple packets per transmission with interleaved data stream
  • Programmable error injection in Verification IP and error detection in design IP
  • Supports flexibility in setting polarity for DPI Interface signals

Application Processor Connectivity and video/command processing

  • DPI or DBI, depending on panel or display unit architecture
  • Generic command support
    • Generic parallel interface for sending and receiving vendor-specific information to and from the display driver logic in the display module
    • Support for all generic read/writes over DBI/Generic interface
  • Video mode support
    • Supports wide range of display resolution and pixel formats
    • Supported display resolutions: QQVGA, QCIF, QVGA, CIF,VGA,WVGA, XGA, 1080p, QXGA, QSXGA
    • Burst mode and non-burst transfers over DPI interface
  • DBI support
    • Supports 8/9/16-bit data transfer in DBI Type B interface
    • Supports all DCS commands

Block Diagram

DSI v1.3 Transmit IP Core block diagram

Benefits

  • Fully compliant to MIPI standard
  • Small footprint
  • Code validated with Spyglass
  • Functionality ensured with comprehensive verification
  • Product quality proven with silicon
  • Premier direct support from Arasan IP core designers

What’s Included?

  • Verilog HDL of the IP Core
  • Synthesis scripts
  • Verification environment
  • User guides for design and verification

Specifications

Identity

Part Number
DSI v1.3 Transmit IP Core
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Arasan Chip Systems Inc.

Learn more about MIPI IP core

MIPI CCI over I3C: Faster Camera Control for SoC Architects

Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.

Vertically Integrated MIPI Solutions

The emerging MIPI standards are designed to ensure interoperability among devices and software that are used in products for the exploding hand-held market. The standards facilitate the interconnection of multiple, mixed-signal integrated circuit devices on a single hand-held product. Use of the standards ensures low power, low pin count and interoperability of all the devices in the system and easy integration.

Frequently asked questions about MIPI IP cores

What is DSI v1.3 Transmit IP Core?

DSI v1.3 Transmit IP Core is a MIPI IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP