Vendor: Arasan Chip Systems Inc. Category: MIPI

MIPI DSI-2 Receiver IP Controller Core

The MIPI Display Serial Interface (DSI-2) Receiver (display panel interface) Controller IP provides a high-speed serial interface…

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Overview

The MIPI Display Serial Interface (DSI-2) Receiver (display panel interface) Controller IP provides a high-speed serial interface between an application processor and display modules using either MIPI C-PHY v1.1 or MIPI D-PHY v1.2 and v2.0.

Key features

Compliant with the following MIPI specifications

  • Display Serial Interface (DSI-2) version 1.0
  • Display Pixel Interface (DPI-2) version 2.00
  • Display Bus Interface (DBI) version 2.00
  • Display Command Set (DCS) version 1.3
  • D-PHY version 1.2
  • D-PHY 2.0 and CPHY 1.1 (Combo PHY)

Block Diagram

MIPI DSI-2 Receiver IP Controller Core block diagram

Benefits

  • Fully compliant to MIPI standard
  • Small footprint
  • Code validated with Spyglass
  • Functionality ensured with comprehensive verification
  • Product quality proven with silicon
  • Premier direct support from Arasan IP core designers

What’s Included?

  • Verilog HDL of the IP Core
  • Synthesis scripts
  • Verification environment
  • User guides for design and verification

Specifications

Identity

Part Number
MIPI DSI-2 Receiver IP Controller Core
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Arasan Chip Systems Inc.

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Frequently asked questions about MIPI IP cores

What is MIPI DSI-2 Receiver IP Controller Core?

MIPI DSI-2 Receiver IP Controller Core is a MIPI IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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