MIPI I3C Basic Slave Controller
MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication.
- I2C / I3C
Low-Speed Control Interface IP cores provide the communication, control, monitoring, and management functions required by modern SoCs, microcontrollers, automotive systems, industrial equipment, and embedded platforms. These interfaces enable reliable connectivity between processors, sensors, peripherals, power-management devices, and external subsystems.
This catalog includes IP solutions for widely adopted control and management protocols such as I2C/I3C, SPI/QSPI/xSPI, UART, CAN, CAN FD, CAN XL, LIN, GPIO, IEEE 1588/PTP, MIPI RFFE, PMBus, Smartcard, ARINC 429, MIL-STD-1553, FlexRay, SENT, HDLC, and other specialized interfaces. Compare controller, target, and protocol IP offerings from multiple vendors based on standards compliance, feature sets, safety support, performance, and integration requirements.
MIPI I3C Basic Slave Controller
MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication.
MIPI I3C Basic Master Controller
MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication.
Low Pin Count (LPC) controller verification IP
The Low Pin Count (LPC) interface is a low bandwidth bus with up to 33 MHz performance.
The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface.
I2C and SPI Master/Slave Controller
The I2CSPI-CTRL is a compact and versatile serial interface controller supporting both SPI (Serial Peripheral Interface) and I2C …
SPI Controller IP- Master/ Slave, Parameterized FIFO, Avalon Bus
The Digital Blocks DB-SPI-MS-AVLN is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave …
SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
The DB-SPI-S-AMBA-BRIDGE is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Slave SPI Bus transfer…
I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
The DB-I2C-S-AHB Controller IP Core interfaces a NIOS II, ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via th…
I2C Controller IP – Master, Parameterized FIFO, Avalon Bus
The DB-I2C-M-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus.
The DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AX…
I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
The DB-I2C-MS-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus in Standard-Mode (100 Kbit/s) …
I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
The DB-I3C-S-REG is an I3C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs requiring the configuration…
I3C Controller IP – I3C / I2C Slave, SCL Clock only, Configure User Registers, no CPU Host Required
The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core focused on low power, low noise, low VLSI footprint ASIC / ASSP desig…
The UART /USART Verification IP provides an effective & efficient way to verify the components interfacing with UART/USART interf…
MIPI I3C Secondary Controller IP core
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …
The I3C Target Lite is a configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivi…
MIPI I3C Basic Secondary Controller
The I3C-SC core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Secondary Controller core compliant with the…
The vendor has designed FlexRay RTL IP Core, supporting data rate up to 10 Mbps.
A Controller Area Network (CAN) is a serial half duplex and differential two-wired asynchronous communication protocol that allow…
The vendor has designed LIN RTL IP Core, supporting data rate up to 20Kbps.