I3C Controller IP – I3C / I2C Slave, SCL Clock only, Configure User Registers, no CPU Host Required

The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core focused on low power, low noise, low VLSI footprint ASIC / ASSP designs requiring the configuration & control of registers with no free running clock. The DB-I3C-S-SCL-CLK-REG processes the I3C protocol & physical layers, and receives & transmits bytes with respect to the I3C payload to / from User Registers within an ASIC / ASSP / FPGA device. The DB-I3C-S-SCL-CLK-REG Controller implements the Slave-Transmit and Slave-Receive protocol according to the MIPI I3C-Basic-Spec-ver1_0 specification.

The DB-I3C-S-SCL-CLK-REG builds on Digital Blocks DB-I2C-S-SCL-CLK Controller and supports I2C Master Slave-Transmit and Slave-Receive protocol according to the Philips I2C-Bus Specification, Version 2.1 as well as the updated NXP Rev .5 October 9, 2012 Specification.

The gigure below depicts the system view of the DB-I3C-S-SCL-CLK-REG Controller IP Core embedded within an ASIC, ASSP or FPGA device. The DB-I3C-S-SCL-CLK-REG Controller receives and transmits data with respect to an external I3C or I2C Master Controller. The DB-I3C-S-SCL-CLK-REG internally interfaces to User Registers / Memory.

• I3C Features
  • I3C Slave Controller - Implements Slave-only protocol for smaller VLSI footprint, for applications requiring Slave–Receiver and Slave–Transmitter capability
  • SCL Clock only for low power, low noise applications requiring configuration & management of User Registers / Memory
  • Autonomous I3C Slave Controller:
    • No local CPU host required
    • No configuring of control/status registers
  • Supports I3C SDR up to 12.5 MHz bus speed
  • I3C 7-bit Dynamic Address Assignment
  • I3C CCC Command Processor
  • Compliance with I3C specification for I3C SDR Slave
    • MIPI Alliance – I3C-Basic-Spec-ver1_0 specification
• I2C Features
  • I2C Slave Controller - Implements Slave-only protocol for smaller VLSI footprint, for applications requiring Slave–Receiver and Slave–Transmitter capability
  • I2C 7- or 10-bit addressing
  • Supports five I2C bus speeds:
    • Standard mode (100 Kb/s)
    • Fast mode (400 Kb/s)
    • Fast mode plus (1 Mbit/s)
    • Ultra fast mode (5 Mbit/s)
    • Hs-mode (3.4 Mbit/s)
  • Compliance with I2C specifications:
    • Philips – The I2C-Bus Specification, Version 2.1, January 2000
    • NXP Rev .5 October 9, 2012
  • Fully-synchronous, synthesizable Verilog RTL core. Easy integration into FPGA or ASIC design flows.

• The DB-I3C-S-SCL-CLK-REG is available in synthesizable RTL Verilog or a technology-specific netlist for FPGAs, along with Synopsys Design Constraints, a simulation test bench with expected results, datasheet, and user manual.