I2C and SPI Master/Slave Controller

The I2CSPI-CTRL is a compact and versatile serial interface controller supporting both SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit) protocols. Its low silicon resource requirement makes it suitable for area-constrained and low-power applications, while its software compatibility with Microchip’s MSSP peripheral eases use and software integration.

In SPI mode, the I2CSPI-CTRL controller can operate as either a controller (master) or target (slave), offering full-duplex communication. In master mode, it initiates data transfers and controls the clock (SCK), while in slave mode, it operates under the control of an external master device. The I2CSPI-CTRL supports configurable clock polarity and operates in the four standard SPI modes (0, 1, 2, 3).

In I2C mode, the I2CSPI-CTRL supports standard and fast mode with transfer rates of up to 400khz, with both 7-bit and 10-bit addressing. It can function as either a master or a slave, with the capability to manage multiple addressing modes and clock stretching. In master mode, the I2CSPI-CTRL initiates communication, sends addresses, and manages data transfer timing. In slave mode, it responds to addresses sent by an external master, acknowledges reception, and sends data upon request. The I2CSPI-CTRL also supports general call addressing and SMBUS protocols, making it suitable for various applications.

The I2CSPI-CTRL core is designed for ease of use and integration and adheres to the industry’s best coding and verification practices. The core’s control and status registers (CSR) are accessed through a 32-bit AMBA® APB interface. The design contains no latches or tri-states and is fully synchronous with a single clock domain making technology mapping straightforward. The I2CSPI-CTRL core is rigorously verified and silicon-proven. It is available in LINT-clean System Verilog source code or as a targeted FPGA netlist. Its deliverables include a testbench, comprehensive documentation, and sample simulation and synthesis scripts.

• Compact and Versatile
  • Only 1.5k gates
  • I2C and SPI Master and Slave
• SPI Interface
  • Compliant with the SPI de facto standard
  • Master/Slave modes
  • Full-Duplex Communication
  • Interrupt Support
  • Configurability
    • Clock Polarity
    • Clock Phase
• I2C Interface
  • Compliant to Philips I2C standard
  • I2C Bus Speeds:
    • Standard-Mode (Sm): up to 100kbit/s, bidirectional
    • Fast-mode (Fm): up to 400kbit/s, bidirectional
  • Master/Slave modes
  • 7-bit and 10-bit addressing
  • Supports single or multi-master buses
  • Clock-Stretching to allow fast-master slow-slave communication
  • SMBUS support
• Easy to Use and Integrate
  • Standardized 32-bit APB interface
  • Single interrupt line with maskable sources
  • Software-compatible with Microchip’s MSSP peripheral
  • Configurable glitch filter
  • Single-clock, LINT-clean design

• Synthesizable System Verilog source code or targeted FPGA netlist
• Testbench and sample test cases
• Simulation and Synthesis scripts
• Documentation