What Amdahl's Law can tell us about multicores and multiprocessing
Embedded.com
Nov 18 2005 (14:00 PM)
Two “laws” have been much on the mind of developers of embedded systems faced with bringing higher levels of performance to designs with strict limits on power: Moore’s Law and the law of diminishing returns
In the mid-60s, Gordon Moore made the observation that component-doubling time on integrated circuits was 12 months, which he later revised to a somewhat slower 24 months. Since then, others have tried to more closely fit his prediction to actual results by changing the doubling interval to 18 months.
This extrapolation has taken on the force of law over the years, despite evidence that as we move toward smaller and smaller geometries that the law of diminishing returns is taking its toll: the tendency for a continuing application of effort or skill toward a particular project or goal to decline in effectiveness after a certain level of result has been achieved.
In the face of this, in order to maintain performance improvements in designs that are severely constrained as to power and space, developers have moved away from the well understood and tested single processor model to system, board and circuit designs with two, three or four processors operating in parallel which they hope will allow them to more efficiently balance power and performance.
But as we make this move, it is important to keep yet another “law” – Gene Amdahl’s – in mind, as a guide to where we can go with this approach, where it is most useful and where it is not.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- What Designers Need to Know About USB Low-Power States
- Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning
- What designers need to know about structural test
- What you need to know about automated testing and simulation
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM