What you need to know about automated testing and simulation
By Kim Pries from Stoneridge Electronics and Jon Quigley from Volvo 3P
Embedded.com Apr 14, 2009 (12:39 PM)
Wedding simulation with automated testing allows test organizations to achieve benefits such as increases in testing speed (through-put), increases in test coverage for both hardware and software, and the ability to test before hardware becomes available. In this article, we will describe each type of approach in turn and then how they can work together synergistically.
Simulation generally refers to a model of a process or function; for example, we can simulate the general behavior of a manufacturing process, a motor vehicle, or any other object for which we have knowledge about inputs, outputs, and behavior.
Both simulation and testing have specific goals. For simulation, we want to facilitate requirements generation, uncover unknown design interactions and details, and reduce development cost by having fewer actual parts.
Much of this activity facilitates testing in quantifying the requirements, making testing more productive (Figure 1, below). For testing, we want to achieve defect containment, reduced product warranty cost, and some level of statistical indication of design readiness.
Figure 1 Simulation Uses
Embedded.com Apr 14, 2009 (12:39 PM)
Wedding simulation with automated testing allows test organizations to achieve benefits such as increases in testing speed (through-put), increases in test coverage for both hardware and software, and the ability to test before hardware becomes available. In this article, we will describe each type of approach in turn and then how they can work together synergistically.
Simulation generally refers to a model of a process or function; for example, we can simulate the general behavior of a manufacturing process, a motor vehicle, or any other object for which we have knowledge about inputs, outputs, and behavior.
Both simulation and testing have specific goals. For simulation, we want to facilitate requirements generation, uncover unknown design interactions and details, and reduce development cost by having fewer actual parts.
Much of this activity facilitates testing in quantifying the requirements, making testing more productive (Figure 1, below). For testing, we want to achieve defect containment, reduced product warranty cost, and some level of statistical indication of design readiness.
Figure 1 Simulation Uses
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- SoC Test and Verification -> Testing mixed-signal Bluetooth designs
- Opto-electronics -> Passive filters upgrade jitter testing
- RF Simulation Improves 802.11a System Performance
- IC Physical Design: Portable Layout and Simulation Technigues for ADSL Analog Devices
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace