How to achieve timing-closure in high-end FPGAs

By Angela Sutton and Jeff Garrison, Synplicity
January 23, 2008 -- pldesignline.com

Using graph-based physical synthesis to achieve timing closure in high-capacity, high-performance FPGAs.

Introduction

Timing-closure is a growing concern for FPGA designers, particularly with the recent introduction of multi-million gate architectures fabricated at the 90 nm and 65 nm technology nodes. It is not sufficient for a timing-closure solution – the entire flow, including synthesis – to meet only the required timing; such a solution must also minimize the number of time-consuming synthesis-place-route iterations and provide results that remain stable across multiple physical synthesis runs and during final routing.

The designers' end goal is to ensure that timing will be met at the end of the FPGA design flow and to implement and debug the FPGA system as quickly and as soon as possible, possibly with the need to incorporate design changes and spec modifications along the way.

Placement and availability of routing resources play a huge role in the designers' ability to meet eventual performance goals in their FPGA implementation. Simultaneous logic synthesis and physical placement optimizations allow designers to rapidly drive towards – and concurrently lock-down – timing performance in their FPGA. The performance is more readily ensured when the synthesis tool passes legalized placement information to the FPGA vendor's back-end tools.

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