Latches and timing closure: a mixed bag
Ashish Goel & Ateet Mishra, Freescale Semiconductor
EETimes (8/2/2011 3:29 PM EDT)
Introduction
Digital blocks contain combinational and sequential circuits. Sequential circuits are the storage cells with outputs that reflect the past sequence of their input values, while output of the combinational circuits depends only on the present input. Latches and flip flops are the commonly used storage elements.
This paper is divided into 4 parts. First part of the paper will discuss the advantages and disadvantages of latches compare to Flip-Flop. Next part describes some unique properties of latches that make them useful in high-frequency design. Third part of the paper will talk about the timing analysis complexities for latch-based design and how to deal with this complexity during the course of design. Finally, the paper will discuss challenges with latch-based design to hierarchical timing closure and partitioning, and some solutions.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions
- Timing Closure on FPGAs
- Deriving design margins for successful timing closure
- Design Rule Violation fixing in timing closure
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs