The verification revolution
Adnan Hamid, Breker Verification Systems
EDN - March 09, 2017
The Accellera Portable Stimulus (PS) standard is expected to be released early this year and that will set the stage for the abstraction of verification to be raised to the system level. While attempts have been made to raise the abstraction used for design, the industry decided to stay at the Register Transfer Level (RTL) for most blocks and instead use a block assembly approach to create systems using internally developed IP or IP coming from third parties. However, verification costs have been rising, and existing verification languages, such as SystemVerilog, and methodologies, including the Universal Verification Methodology (UVM) fail to address issues associated with system-level verification. Thus, the stage was set for the development of a new system level verification methodology.
Portable Stimulus is the first true verification language, in that it does not focus on the direct creation of stimulus like previous generations. It is a description of verification intent, encapsulated in a mixture of C++ and graphs. Tools transform that verification intent model into fully self-checking scenarios run on the design in a simulator or emulator. This process is very similar to the notions of synthesis being applied to a design model, except the output from the tool is a verification test case. While test case synthesis is the first application under consideration for PS, many other applications will be possible. The verification intent model is also a natural place to collect coverage data, but first the industry has to decide what coverage means at the system level.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- IC design: A short primer on the formal methods-based verification
- A Survey on SoC Security Verification Methods at the Pre-silicon Stage
- IFV: Information Flow Verification at the Pre-silicon Stage Utilizing Static-Formal Methodology
- Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices