The challenges of nextgen multicore networks-on-chip systems: Part 1

By Luca Benini and Giovanni De Micheli
Feb 5 2007 (0:15 AM), Embedded.com

The reason for the growing interest in networks on chips (NoCs) can be explained by looking at the evolution of integrated circuit technology and at the ever-increasing requirements of electronic systems. The integrated microprocessor has been a landmark in the evolution of computing technology.

Whereas it took monstrous efforts to be completed, it appears now as a simple object to us. Indeed, the microprocessor involved the connection of a computational engine to a layered memory system, and this was achieved using busses. In the last decade, the frontiers of integrated circuit design opened widely. On one side, complex application specific integrated circuits (ASICs)were designed to address-speciýc applications, for example mobile telephony.

These systems require functional units, thus requiring efficient on-chip communication. On another side, multiprocessing platforms were developed to address high-performance computation, such as image rendering. Examples are Sony's emotion engine [25] and IBM's cell chip [26], where on-chip communication efficiency is key to the overall system performance.
At the same time, the shrinking of processing technology in the deep submicron (DSM) domain exacerbated the imbalance between gate delays and wire delays on chip. Accurate physical design became the bottleneck for design closure, a word in jargon to indicate the ability to conclude successfully a tape out. Thus, the on-chip interconnection is now the dominant factor in determining performance. Architecting the interconnect level at a higher abstraction level is a key factor for system design.

We have to understand the introduction of NoCs in systems-on-chip (SoCs) design as a gradual process, namely as an evolution of bus interconnect technology. For example, there is not a strict distinction between multi-layer busses and crossbar NoCs. We have also to credit C. Seitz and W. Dally [9] for stressing the need of network interconnect for high-performance multiprocessing, and for realizing the ýrst prototypes of networked integrated multiprocessors.

But overall, NoC has become a broad topic of research and development in the new millennium, when designers were confronted with technological limitations, rising hardware design costs and increasingly higher system complexity.

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