Debugging FPGA-based video systems: Part 1

Andrew Draper, Altera Corp.
Embedded.com (May 27, 2013)

In this series of articles we will discuss some strategies for debugging a video system built in an FPGA. The examples use Altera’s video debugging tools and methodology, although the concepts can be applied generally.

Before moving on to the video-specific parts of debugging it is worth checking that the design has synthesized correctly and has passed a number of basic sanity checks.

Timing Analysis

Hardware designs that run from a clock need to meet a number of timing constraints. The two most basic of these exist to prevent errors if a signal changes while it is being sampled by a register: The input to a register must be stable for a time before the clock edge on which it is sampled e referred to as the setup time.

To read the full article, click here