Tackling test challenges for low-power design

Chris Hawkins from ARM & Jason Doege and George Kuo from Cadence
EE Times
(11/07/2005 9:00 AM EST)

With the move to advanced process technologies, concerns over device power once largely limited to specialized markets have escalated rapidly among mainstream designers.

More semiconductor companies are adopting low-power design strategies that combine multiple supply voltages, voltage scaling, extensive clock gating coverage and other techniques that push performance and increase complexity of device operating modes. In turn, this growing interest in power management techniques in design dictates a growing need for increased attention to power concerns in test and greater urgency for more effective design for test (DFT) methods for low-power designs.

Power has become a premium across mainstream applications ranging in diversity from battery-powered personal appliances to multiprocessor server farms. For designers, power management means controlling leakage power lost during standby mode, as well as dynamic power consumption when multiple transistors switch in unison to perform desired functions.

Designers address increased leakage current at more advanced nanometer technologies through techniques such as multi-voltage supply design, using lower supply voltage domains where possible. In turn, design teams must address test issues associated with increased use of non-functional elements such as level shifter cells.

For control of dynamic power, designers use clock gating methods to turn off unnecessary registers and minimize the number of transistors that need to switch at any one time. Clock gating can significantly complicate fault isolation and fault observability, and the continued trend toward low-power design promises to heighten this challenge to test. While a typical design might have fewer than 30% of its registers involved in clock gating, as many as 85% of all registers can be clock gated in low-power designs, and designers are likely to push this percentage even higher.

At the same time, low-power operation introduces new types of device defects. In particular, complex circuits face increased risk from delay-related failures in low-power modes. Designs that are particularly optimized for low-power suffer from lower noise margins due to the combination of increased uncertainty in clocks and lower average slack (Figure 1). As a result, design teams are now seeing a greater occurrence of multi-mode timing paths that would pass in higher voltage modes fail in their low-power operating modes.

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