System synchronization styles and trends
Sandeep Srinivasan, Synchronous Design Automation
Eby G. Friedman, University of Rochester, New York
(03/06/2006 9:00 AM EST), EE Times
This article describes emerging trends in synchronizing digital ICs and shows how process scaling, rapid increases in clock frequencies, and demand for lower power dissipation will affect the choice of synchronization styles going forward.
System synchronization controls the flow of events in a system. In the same manner that all signals are, in reality, analog in nature, all timing is in reality asynchronous. Despite this characteristic, local timing constraints can be placed on a system to permit the system to behave as if the system is completely synchronous.
This strategy uses a central clock signal to control the relative timing of events and is called synchronous clocking. Fully synchronous clocking makes it easier to understand the temporal behavior of events in a hardware system with reference to a clock edge.
Eby G. Friedman, University of Rochester, New York
(03/06/2006 9:00 AM EST), EE Times
This article describes emerging trends in synchronizing digital ICs and shows how process scaling, rapid increases in clock frequencies, and demand for lower power dissipation will affect the choice of synchronization styles going forward.
System synchronization controls the flow of events in a system. In the same manner that all signals are, in reality, analog in nature, all timing is in reality asynchronous. Despite this characteristic, local timing constraints can be placed on a system to permit the system to behave as if the system is completely synchronous.
This strategy uses a central clock signal to control the relative timing of events and is called synchronous clocking. Fully synchronous clocking makes it easier to understand the temporal behavior of events in a hardware system with reference to a clock edge.
To read the full article, click here
Related Semiconductor IP
- Secure Boot Loader
- Memory Subsystem
- 4/8-bit mixed-precision NPU IP
- Compiler-centric single-core LPU
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Related Articles
- Using IEEE-1588 transparent clocks to improve system time synchronization accuracy
- Algorithmic delay and synchronization in MPEG audio codecs
- Emerging Trends and Challenges in Embedded System Design
- New Realities Demand a New Approach to System Verification and Validation
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection