Algorithmic delay and synchronization in MPEG audio codecs
By Ranjani H G and Ameet Kalagi, Ittiam Systems Pvt Ltd
Audio DesignLine (05/05/10, 02:26:00 PM EDT)
Introduction
A variety of audio compression technologies are being used today, each having a distinct advantage over the other in terms of compression ratio, coding delay, coding complexity or legacy system compatibility. This makes subset of audio codecs suited for particular systems and makes working with multiple audio compression technologies indispensable.
In designing time-critical systems like conferencing, broadcast transcoding systems or be it in designing any audio and video play-out system, the knowledge of the delay encountered while audio encoding or decoding becomes critical.
Figure 1: Audio Delay encountered in systems
Figure 1 tries to capture the various stages at which audio data encounters delay in different applications and systems.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- MPEG Standards -> Streaming audio needs interoperability
- Paving the way for the next generation audio codec for the True Wireless Stereo (TWS) applications - PART 1 : TWS challenges explained
- Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - PART 2 : Increasing play time
- Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - PART 3 : Optimizing latency key factor
Latest Articles
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety