Using IEEE-1588 transparent clocks to improve system time synchronization accuracy
By Paul Skoog, Symmetricom, Inc.
Embedded.com (11/24/09, 08:25:00 PM EST)
Simply put, time synchronization is setting the time on two or more clocks to be the same. Hidden in this simple sentence are obstacles involved with "setting" the time, the length of time it takes to "set" the time and the varying levels of acceptance of what the "same" time actually is. Just the notion of "same time" conjures up accuracy to the second, millisecond, microsecond, nanosecond, or better.
Key to understanding synchronization is that clocks drift and need to be corrected periodically. This begs the questions, "How long are they 'the same' before they are not 'the same' as they drift apart?"
It takes time to go through the process of correcting the time, and during this process how accurate can we set the time relative to another clock in the first place? This process of correcting the time is challenging and is a limiting factor in how accurately two clocks can be synchronized.
IEEE-1588 defines a process of transferring time. However, before jumping in and demonstrating that Transparent Clocks (aka IEEE-1588 enabled switches) work great to improve IEEE-1588 time transfer accuracy, there are a few fundamentals we need to cover along the lines of offsets and delays and how switches and routers contribute to both.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- Embedded Systems -> Real-time OS takes 'time' seriously
- Reconfigurable processors make move into big time
- SoC Configurable Platforms -> Network synchronization relies on CSoC
- On-time Finish Rests With Multiple Clocks
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM