New Realities Demand a New Approach to System Verification and Validation

By Vijay Chobisa, Siemens
EETimes Europe (November 22, 2024)

The landscape for advanced chip design is changing dramatically and demands new approaches to verification and validation.

The landscape for advanced chip design is changing dramatically and demands new approaches to verification and validation. Many of the most ambitious designs are developed inside system houses at advanced process nodes and larger gate counts. These designs depend ond sophisticated on-die networks, pools of static random-access memory (SRAM), and complex power, clock and test architectures. Perhaps the most striking change concerns their applications, which include AI acceleration, high-performance compute, and networking and communications. They are used exclusively by the systems house, often in one specific hardware environment and frequently with a specific software workload.

System-specific chip designs require verification that focuses on ensuring the system works. Engineers use conventional register-transfer level (RTL) verification and validation of the entire system to prove correct operation of the full software stack and application code. They employ verification that checks interactions between the chip and its board, and possibly with the mechanical subsystems within the overall design.

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