New Realities Demand a New Approach to System Verification and Validation
By Vijay Chobisa, Siemens
EETimes Europe (November 22, 2024)
The landscape for advanced chip design is changing dramatically and demands new approaches to verification and validation.
The landscape for advanced chip design is changing dramatically and demands new approaches to verification and validation. Many of the most ambitious designs are developed inside system houses at advanced process nodes and larger gate counts. These designs depend ond sophisticated on-die networks, pools of static random-access memory (SRAM), and complex power, clock and test architectures. Perhaps the most striking change concerns their applications, which include AI acceleration, high-performance compute, and networking and communications. They are used exclusively by the systems house, often in one specific hardware environment and frequently with a specific software workload.
System-specific chip designs require verification that focuses on ensuring the system works. Engineers use conventional register-transfer level (RTL) verification and validation of the entire system to prove correct operation of the full software stack and application code. They employ verification that checks interactions between the chip and its board, and possibly with the mechanical subsystems within the overall design.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- A New Approach to In-System Silicon Validation and Debug
- A new approach to improving system performance
- How FPGA technology is evolving to meet new mid-range system requirements
- BCD Technology: A Unified Approach to Analog, Digital, and Power Design
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace