Plan your verification with SystemVerilog
Thomas L. Anderson, Cadence Design Systems
(02/19/2007 9:00 AM EST) -- EE Times
As verification engineers move to more-sophisticated techniques for system-on-chip (SoC) designs, their planning process is evolving as well. Traditional test-based planning is being supplanted by more sophisticated verification plans tracking coverage and assertions. One factor in this change is the widespread adoption of SystemVerilog, which supports the specification of functional coverage points, assertions and testbench constraints. The increasing use of constrained-random testbenches as an alternative to hand-written tests is another major factor.
Traditionally, the verification process entailed identifying all the important features in the design, defining a set of directed tests to verify the features, writing the tests by hand, and running and debugging the tests in simulation. This approach works well for small designs, but SoC devices require thousands of handwritten directed tests to verify all the features. Hiring limitations, time-to-market pressures and the sheer tedium of writing tests all mean that a better technique is required. Constrained-random testbenches require the verification team to specify constraints that define the rules for the design inputs.
Once this setup work is done, a testbench automation tool or simulator can generate input stimulus to exercise the design. Variations in the generated tests can be introduced by altering the constraints, selecting different random seeds or biasing the values generated for the inputs. SystemVerilog provides the constructs necessary to define constraints, seeds and biases.
Evolving from directed to constrained-random tests requires a corresponding change in the verification planning process. A traditional test plan includes a list of features for the design, the tests to verify each feature and the status of the test. As tests are written, run and debugged, their status is updated in the verification plan. That plan might be maintained by hand in the form of a document or spreadsheet, or it might be updated automatically as part of a verification process automation (VPA) flow.
(02/19/2007 9:00 AM EST) -- EE Times
As verification engineers move to more-sophisticated techniques for system-on-chip (SoC) designs, their planning process is evolving as well. Traditional test-based planning is being supplanted by more sophisticated verification plans tracking coverage and assertions. One factor in this change is the widespread adoption of SystemVerilog, which supports the specification of functional coverage points, assertions and testbench constraints. The increasing use of constrained-random testbenches as an alternative to hand-written tests is another major factor.
Traditionally, the verification process entailed identifying all the important features in the design, defining a set of directed tests to verify the features, writing the tests by hand, and running and debugging the tests in simulation. This approach works well for small designs, but SoC devices require thousands of handwritten directed tests to verify all the features. Hiring limitations, time-to-market pressures and the sheer tedium of writing tests all mean that a better technique is required. Constrained-random testbenches require the verification team to specify constraints that define the rules for the design inputs.
Once this setup work is done, a testbench automation tool or simulator can generate input stimulus to exercise the design. Variations in the generated tests can be introduced by altering the constraints, selecting different random seeds or biasing the values generated for the inputs. SystemVerilog provides the constructs necessary to define constraints, seeds and biases.
Evolving from directed to constrained-random tests requires a corresponding change in the verification planning process. A traditional test plan includes a list of features for the design, the tests to verify each feature and the status of the test. As tests are written, run and debugged, their status is updated in the verification plan. That plan might be maintained by hand in the form of a document or spreadsheet, or it might be updated automatically as part of a verification process automation (VPA) flow.
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