Making Verification Methodology and Tool Decisions
This is the second of a three parts series. Part 1 can be found here
Are you itching to try a new methodology or technology to enhance your existing processes? Are you certain that management will resist change? Read on and learn how to use the new field of metric-driven engineering to objectively justify your decisions using automatically gathered data.
It happens all the time in engineering. A new process or methodology comes along. It looks attractive, your gut tells you this is the way to go, but adopting it requires one the big three 'scary' things:
- Risk (We've never done this before, will it work?)
- Cultural change (You want my designers to write assertions?)
- Spending money (Are you sure that tool will pay for itself?)
What you need to justify your decision are objectively measured results. Maybe you try the new technique on a pilot project and it works 'well'. But how do you quantify 'well' to upper management? You could keep detailed measurements of the time spent on each step of the new process. What a pain though! Simply measuring and recording the time used could significantly impact the effectiveness of the process. What if you could automatically measure the effectiveness of the new technique?
Related Semiconductor IP
- Secure Boot Loader
- Memory Subsystem
- 4/8-bit mixed-precision NPU IP
- Compiler-centric single-core LPU
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Related Articles
- Efficient methodology for verification of Dynamic Frequency Scaling of clocks in SoC
- Metric Driven Verification of Reconfigurable Memory Controller IPs Using UVM Methodology for Improved Verification Effectiveness and Reusability
- Efficient methodology for design and verification of Memory ECC error management logic in safety critical SoCs
- Methodology Independent Exhaustive Constraint Solver for Random Verification and Regression Generation
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection