How to get the best performance and utilization from Xilinx Virtex-5 FPGAs

By Dr. Angela Sutton, Synplicity
pldesignline.com -- September 13, 2006

In order to obtain the best performance and efficiently utilize the capacity offered by Virtex-5 FPGAs, it is necessary to use the right synthesis technology.

Xilinx recently introduced a state-of-the-art family of next-generation FPGAs with a host of new architectural features. In order to take full advantage of these new features, Synplicity was provided with early access to the new architecture, and – by the time the new devices were introduced to the market – engineers at Synplicity and Xilinx had been working side-by-side for almost a year to enhance Synplicity's Synplify Pro synthesis engine.

The world's first FPGAs to be fabricated at the 65 nm technology node, the Virtex-5 family from Xilinx provides 65% more logic cells and 25% more input/outputs (I/Os) as compared to the preceding Virtex-4 generation of devices. At the same time, members of the Virtex-5 family provide 30% higher performance, 35% lower dynamic power dissipation, and they consume 45% less silicon real estate as compared to their Virtex-4 counterparts.

Virtex-5 FPGAs boast a wide range of new architectural features, such as 6-input lookup tables (LUTS) and a new diagonal interconnect fabric (traditional architectures employ only 4-input LUTs and conventional orthogonal interconnect). Virtex-5 devices also feature high-speed, high-capacity, high-performance RAM, DSP, and clock management hard IP blocks tuned for 550 MHz operation. Additional hard IP – such as integrated FIFO support in the RAM blocks – helps to further reduce dynamic power consumption.

Increases in the complexity of the FPGA fabric demand corresponding increases in the sophistication of the synthesis algorithms. If the same algorithms used for a fabric based on 4-input LUTs were applied to a fabric with 6-input LUTs, for example, then synthesis runtimes could easily be orders of magnitude longer. This means that in order to take full advantage of the specialized architectural features found in the Virtex-5 family, synthesis algorithms have to be fine-tuned or – in many cases – completely re-crafted.

The Virtex-5 family includes devices with up to 330,000 logic cells, 10 megabytes of on-chip memory, 1,200 general-purpose input/outputs (I/Os), and a host of additional hardened intellectual property (IP) blocks. Future platforms will provide even greater densities and capabilities further expanding the reach of advanced FPGA architectures across a wide range of application domains. In order to address the demands of these extreme FPGA devices, Synplicity and Xilinx have formed a joint Ultra-High-Capacity Timing Closure task force. The purpose of this task force is for engineering teams from both companies to collaborate to define and implement new design flows that maximize design productivity and the quality of results for ultra-high-density designs implemented using these next-generation FPGAs.

Below we introduce some of the key features associated with the new Virtex-5 family of devices and discuss how Synplicity's Synplify Pro FPGA synthesis technology has been enhanced to take advantage of the capabilities provided by these new components.

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