How to get more performance in 65 nm FPGA designs

By Adrian Cosoroaba and Frederic Rivoallon, Xilinx
November 07, 2006

This ''How To'' explores how FPGA designers can benefit from the latest FPGA building blocks in their quest for higher system-level performance.
 
Getting the most performance out of today's FPGA designs grows ever more challenging as system complexities increase and functional requirements become more demanding. Maximizing system performance in an FPGA system design requires a balanced mix of performance-efficient components comprising logic fabric, on-chip memory, DSP blocks, and I/O bandwidth. This article explores how FPGA designers can benefit from the latest FPGA building blocks in their quest for higher system-level performance. We will explore key features of new 65 nm fabric architecture with examples that quantify the anticipated performance improvements for logic and arithmetic functions.

Hard IP blocks are essential in sustaining a desired performance level that may be limited by potential bottlenecks outside of the fabric, like on-chip memory buffers, DSP blocks or I/Os. Analysis of various design benchmarks are provided to better understand the impact of new product and technology innovations and to better quantify expectations.

Extracting maximum performance from an FPGA design also depends heavily on the ability of software tools to optimally map the RTL code onto the FPGA technology cells. Tuning the design with the latest software options requires squeezing more MHz or Mbps from the design implementation. This article provides actual examples on how the latest physical synthesis options can make a difference in meeting timing requirements.

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