Get multicore performance from one core
By Kevin D. Kissell and Pete Del Vecchio, MIPS Technologies
Apr 18 2007 (0:15 AM), Embedded Systems Design
System-on-chip (SoC) designers know what it's like to do more with less. They're constantly challenged by ever-increasing constraints on system cost and power consumption while being tasked with increasing the performance and functionality of their designs. The tricks of the trade available to designers are, at best, a set of difficult trade-offs.
For example, some designers ramp up the processor's clock speed, but this approach usually results in higher power consumption. In addition, memory performance hasn't kept pace with processor technology, as Figure 1 illustrates, and this mismatch limits any significant gains in system performance. A multicore system is another option, but this suffers from a larger die area and higher cost. Any performance increase comes at a fairly substantial cost in silicon and system power.
Apr 18 2007 (0:15 AM), Embedded Systems Design
System-on-chip (SoC) designers know what it's like to do more with less. They're constantly challenged by ever-increasing constraints on system cost and power consumption while being tasked with increasing the performance and functionality of their designs. The tricks of the trade available to designers are, at best, a set of difficult trade-offs.
For example, some designers ramp up the processor's clock speed, but this approach usually results in higher power consumption. In addition, memory performance hasn't kept pace with processor technology, as Figure 1 illustrates, and this mismatch limits any significant gains in system performance. A multicore system is another option, but this suffers from a larger die area and higher cost. Any performance increase comes at a fairly substantial cost in silicon and system power.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- How to get the best performance and utilization from Xilinx Virtex-5 FPGAs
- Achieving multicore performance in a single core SoC design using a multi-threaded virtual multiprocessor: Part 2
- A Flexible, Low Power, High Performance DSP IP Core for Programmable Systems-on-Chip
- Putting multicore processing in context: Part One
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow