Growth forecast for semiconductor design business
Growth forecast for semiconductor design business
By Chris Edwards, EE Times UK
September 17, 2001 (6:09 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010917S0021
Future Horizons has forecast strong growth for the design house and fabless semiconductor industry in Europe, but warns that the number of companies in the market is likely to fall from today's 170. According to the company's report on the European IC design and fabless IC industry, the UK has a commanding lead in terms of number of companies and revenues, led by ARM Holdings and Tality. Speaking at the company's annual mid-term semiconductor industry briefing seminar, Chris Ryan, industry analyst for Future Horizons, said the European independent design market will grow from $2.5bn this year to $8.3bn in 2005. But Malcolm Penn, Future Horizons' chairman and CEO, warns that the number of companies in the market will fall sharply during the next four years. "It will be like the gate array design business," said Penn. "If you take yourself back to 1980 and look at the number of gate array companies in the UK. Ten years later it had boiled itself down to a hard core. You cannot expect 160 or 170 companies to be sustained. There will only be about three ARMs and a lot of others who won't make it." The company looked at the revenue per design engineer for firms working in the sector and found that those with the lowest are in the system-on-chip (SoC) contract design and intellectual property sectors. Those revenues fell from 1999 to 2000. "We saw trouble for the SoC people in terms of the high cost of engineering, but maybe they have no other costs," said Ryan.
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- An Outline of the Semiconductor Chip Design Flow
- Reliability challenges in 3D IC semiconductor design
- The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization
- FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM