Efficient Magnetization Switching via Orbital-to-Spin Conversion in Cr/W-Based Heterostructures
A highly efficient spin–orbit torque (SOT) switching mechanism is crucial for the realization of practical SOT magnetic random-access memory (MRAM). This study proposes a Cr/W-based spin current source (SCS) that harvests the sizable orbital current from resistive Cr and results in an additional SOT through the orbital-to-spin conversion via the adjacent thin W layer. The optimal damping-like SOT efficiency can be up to −0.30 for the Cr/W heterostructure and −0.32 for the Cr/W multilayer, both of which outperform the traditional resistive W with a baseline SOT efficiency of −0.23. Additionally, the resistivity dependence of the apparent spin–orbital Hall conductivity reveals that using highly resistive Cr (>400 μΩ·cm) is the key to generating efficient orbital currents. In the cases of Cr/W heterostructure and Cr/W multilayer structures, the largely improved efficiencies also contribute to an ultralow current magnetization switching with zero-thermal current density of 1.88 and 1.54 MA/cm2, expanding the utility of W-based SOT devices in high-efficiency and low-power memory applications.
To read the full article, click here
Related Semiconductor IP
- MRAM Memory Model
- MRAM Synthesizable Transactor
- AMBA SPI Controller MRAM Controller
- Power and Clock Generation IP - GLOBALFOUNDRIES® 22FDX®
- AI/ML Accelerator
Related Articles
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- Taking Cryptography Out of the Data Path via Near-Memory Processing in DRAM
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices