Analysis: CEVA's ''Lite'' Mobile Multimedia Platform

In March CEVA unveiled "Mobile-Media-Lite" (MMLite), a family of multimedia processing solutions comprising licensable silicon IP and software. The family is aimed at low-end multimedia-enabled devices such as mobile TV players, portable multimedia players, and multimedia phones. CEVA also announced the first family member, the MM2200, a single-processor multimedia engine (shown in Figure 1). CEVA's intent is to provide highly integrated, application-optimized solutions; the company states that the MM2200 is area and energy optimized for cost-constrained consumer electronics products.
Figure 1. Block diagram of the MM2200 hardware platform.
The MM2200, like CEVA's earlier MM2000 platform, is based on the CEVA-X1620 DSP core (see BDTI's analysis excerpts and benchmark scores), and features a DMA engine and peripherals. Like the MM2000, the MM2200 also includes a range of optimized software for video, audio, imaging, and voice encoding and decoding; audio/video synchronization, file parsing, and protocol encoding/decoding; video conferencing, and media player and recorder functionality. However, unlike the MM2000, which targets mid- to high-end multimedia applications, the MM2200 is specialized for low-end multimedia—it has less memory, fewer peripherals, and lower performance. With both platforms, CEVA offers single-core, programmable, application-optimized engines.
For more BDTI analysis of CEVA's offering, see the full article at InsideDSP.
Related Semiconductor IP
- Secure Boot Loader
- Memory Subsystem
- 4/8-bit mixed-precision NPU IP
- Compiler-centric single-core LPU
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Related Articles
- PowerVR MBX - Creating an IP standard for advanced mobile multimedia
- Mobile apps should be developed with platform independence
- Analysis: CEVA's 32-bit, Dual-MAC TeakLite-III DSP
- Analysis: ZSP800 and VZ.AudioHD platform
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection