Analysis: CEVA's 32-bit, Dual-MAC TeakLite-III DSP

July 25, 2007

On May 31, CEVA Inc. announced CEVA-TeakLite-III, a new family of DSP cores. The TeakLite-III cores build upon CEVA's earlier TeakLite cores, CEVA-TeakLite and CEVA-TeakLite-II, with which the TeakLite-III is backwards compatible. To meet the precision and throughput demands of its intended applications, which include high-end audio, 3G cellular, VoIP, and portable audio players, the TeakLite-III features support for both 32-bit and 16-bit fixed-point data, and increased MAC throughput relative to the earlier TeakLite cores.

The TeakLite-III features two 16-bit MAC units and one 32-bit MAC unit, compared to one 16-bit MAC unit in earlier TeakLite cores. It adds support for parallel execution of certain instructions, such as a MAC and some load/store instructions; and for predicated execution of instructions to accelerate decision-making code. The TeakLite-III also features a longer pipeline, which CEVA claims will enable clock speeds of up to 350 MHz in a 90 nm process; CEVA's earlier TeakLite cores topped out at 245 MHz. These enhancements should give the TeakLite-III a significant edge over earlier TeakLite cores on many DSP applications. (Cited clock speeds assume a 90 nm G process and worst-case process, voltage, and temperature.) In addition, the TeakLite-III features accelerators for Huffman coding, FFT and Viterbi algorithms. These accelerators should further boost performance of the TeakLite-III relative to earlier TeakLite cores—CEVA's initial performance estimates suggest a 2x boost on audio tasks, considering instruction set enhancements alone.

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