Ethernet MAC 100G/200G/400G/800G/1.6T

The Chip Interfaces 100G/200G/400G/800/1.6T Ethernet Media Access Control (MAC) IP core provides a comprehensive and flexible solution for implementing the IEEE 802.3 MAC layer for high-speed Ethernet required in demanding applications such as hyperscale data centers, high-performance computing (HPC), and Artificial Intelligence (AI) / Machine Learning (ML) clusters.

Designed for ASIC targets, this IP core enables seamless integration into next-generation networking equipment operating at 100 Gbps to 1.6 Tbps data rates. Compliant with the IEEE 802.3 standard, the Comcores MAC IP ensures interoperability while offering features optimized for low latency and high throughput. The core is highly configurable and easy interfacing with Chip Interfaces 100G to 1.6T PCS solutions.

For the client side, the IP core uses a multichannel MAC scheme to guarantee line-speed operation across all Ethernet packet sizes. The TDM interfacing scheme ensures the packet order is maintained for each MAC channel as well as across all MAC channels. The core implements a flexible bit width Channelized AXI Stream Client interface for 100 Gbps to 1.6 Tbps operation. A multi-channel TDM nGMII interface towards the PCS is available but can also be replaced with De-mux logic to interface to standard nGMII ports towards multiple PCS blocks.

Delivers Performance

• Designed to IEEE 802.3-2022 and IEEE 802.3dj specification
• Low latency and compact implementation
• Full duplex Ethernet interfaces

Highly Configurable

• Flexible width TDM AXI-Stream interface
• Comes with nbit TDM or parallel GMII as PMA interface

Feature Rich

• Deficit Idle Count for maximum data throughput supported
• FCS generation supported
• Optional statistics gathering
• Jumbo frames support

Silicon Agnostic

• Designed in SystemVerilog and targeting ASICs

Test Environment

• Ethernet MAC 100G-1.6T IP is Tested against a VIP model in UVM regression for full functional coverage

Silicon Agnostic

• Designed in Verilog and targeting both ASICs and FPGAs

PHY Integration

• PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient  deployment

Active Support

• All support is actively provided by engineers directly

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

• Solid documentation, including User Manual, Release Note and Quick Start Guide.
• Simulation Environment, including Simple Testbed, Test case, Test Script.
• Timing Constraints in Synopsys SDC format.
• Access to support system and direct support from Chip Interfaces Engineers.
• Test Report , Synopsys SGDC Files and Synopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request