Formal property verification: A tale of two methods

David Vincenzoni, STMicroelectronics
EDN (January 15, 2018)

The Formal Property Verification (FPV) methodology often gets used in the last step of verification flow, after much time spent building a complex random constrained UVM (Universal Verification Methodology) environment where some corner cases are still not covered.

Other times, FPV is used when a silicon bug is found that was not raised during the dynamic verification phase.

In a wisely applied verification flow, FPV should be used in the first phase, as soon as the RTL (Register Transfer Logic) code is available.

Here we look at two examples of verification flow:

• A digital block verified through a UVM test bench
• Then, first verified using FPV flow.

To read the full article, click here