Formal Verification Has It Covered!
Dave Kelf, OneSpin Solutions
EETimes (7/14/2017 02:41 PM EDT)
Reducing the risk of malfunctions that could ultimately lead to the physical harm of road users is a huge challenge. That's why many of the auto makers turn to formal verification.
The automotive industry is undergoing a period of rapid and disruptive transformations. Apparently, self-driving cars will be ready for urban ride-sharing fleets and equipped with no steering wheel or pedals by 2021. Vehicle-to-everything connectivity, autonomous driving, a new generation of human-machine interfaces and new industry players will bring a level of unprecedented creativity and innovation.
Innovation brings on new challenges. Chip verification design engineers of automotive and other mission-critical applications are facing two fresh challenges –– safety and security. The New York Times recently reported that security experts are in high demand with automobile manufacturers to help tackle cybersecurity threats. Security experts have it covered!
To read the full article, click here
Related Semiconductor IP
- Mesochronous Bridge for PCIe/CXL
- AI-native GPU
- OpenGMSL Verification IP
- OpenGMSL Leaf IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
Related Articles
- Formal verification: where to use it and why
- Viewpoint: Formal verification with constraints - It doesn't have to be like tightrope walking
- How formal verification saves time in digital IP design
- Don't over-constrain in formal property verification (FPV) flows
Latest Articles
- FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity
- MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators
- Analog Pin Directionality as an Exfiltration Attack Surface in Mixed-Signal ICs
- SIMT-Aware Lockstep Verification and Functional-Coverage Closure Methodology for an Open-Source RISC-V GPGPU: A UVM 1.2 Environment
- Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing