40G UCIe IP Advantages for AI Applications
By Aparna Tarde, Sr. Technical Product Manager and Manuel Mota, Sr. Product Manager - Synopsys
The deployment of generative AI in the devices we use every day is growing, driving demand for large language model sizes and higher compute performance. According to a presentation by Yole Group at the 2024 OCP Regional Summit, ‘For training on GPT-3 with 175 billion parameters, we estimate that between 6,000 and 8,000 A100 GPUs would have required up to a month to complete.’ Growing HPC and AI compute performance requirements are driving the deployment of multi-die designs, integrating multiple heterogeneous or homogenous dies in a single standard or advanced package. For AI workloads to be processed reliably at a fast rate, the die-to-die interface in multi-die designs must be robust, low latency, and most importantly high bandwidth. This article outlines the need for 40G UCIe IP in AI data center chips leveraging multi-die designs.
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Related Semiconductor IP
- UCIe IP Core
- Verification IP for UCIe
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- UCIe 3.x Controller IP
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